MuTARe : a multi-target, adaptive reconfigurable architecture

Detalhes bibliográficos
Autor(a) principal: Brandalero, Marcelo
Data de Publicação: 2019
Tipo de documento: Tese
Idioma: eng
Título da fonte: Biblioteca Digital de Teses e Dissertações da UFRGS
Texto Completo: http://hdl.handle.net/10183/212551
Resumo: Power consumption, earlier a design constraint only in embedded systems, has become the major driver for architectural optimizations in all domains, from the cloud to the edge. Application-specific accelerators provide a low-power processing solution by efficiently matching the hardware to the application; however, since in many domains the hardware must execute efficiently a broad range of fast-evolving applications, unpredictable at design time and each with distinct resource requirements, alternatives approaches are required. Besides that, the same hardware must also adapt the computational power at run time to the system status and workload sizes. To address these issues, this thesis presents a general-purpose reconfigurable accelerator that can be coupled to a heterogeneous set of cores and supports Dynamic Voltage and Frequency Scaling (DVFS), synergistically combining the techniques for a better match between different applications and hardware when compared to current designs. The resulting architecture, MuTARe, provides a coarse-grained regular and reconfigurable structure which is suitable for automatic acceleration of deployed code through dynamic binary translation. In extension to that, the structure of MuTARe is further leveraged to apply two emerging computing paradigms that can boost the power-efficiency: Near-Threshold Voltage (NTV) computing (while still supporting transparent acceleration) and Approximate Computing (AxC). Compared to a traditional heterogeneous system with DVFS support, the base MuTARe architecture can automatically improve the execution time by up to 1:3 , or adapt to the same task deadline with 1:6 smaller energy consumption, or adapt to the same low energy budget with 2:3 better performance. In NTV mode, MuTARe can transparently save further 30% energy in memory-intensive workloads by operating the combinatorial datapath at half the memory frequency. In AxC mode, MuTARe can further improve power savings by up to 50% by leveraging approximate functional units for arithmetic computations.
id URGS_28f9b17297873f2304a8e5906ceb24ec
oai_identifier_str oai:www.lume.ufrgs.br:10183/212551
network_acronym_str URGS
network_name_str Biblioteca Digital de Teses e Dissertações da UFRGS
repository_id_str 1853
spelling Brandalero, MarceloBeck Filho, Antonio Carlos SchneiderCarro, Luigi2020-08-01T03:59:43Z2019http://hdl.handle.net/10183/212551001093309Power consumption, earlier a design constraint only in embedded systems, has become the major driver for architectural optimizations in all domains, from the cloud to the edge. Application-specific accelerators provide a low-power processing solution by efficiently matching the hardware to the application; however, since in many domains the hardware must execute efficiently a broad range of fast-evolving applications, unpredictable at design time and each with distinct resource requirements, alternatives approaches are required. Besides that, the same hardware must also adapt the computational power at run time to the system status and workload sizes. To address these issues, this thesis presents a general-purpose reconfigurable accelerator that can be coupled to a heterogeneous set of cores and supports Dynamic Voltage and Frequency Scaling (DVFS), synergistically combining the techniques for a better match between different applications and hardware when compared to current designs. The resulting architecture, MuTARe, provides a coarse-grained regular and reconfigurable structure which is suitable for automatic acceleration of deployed code through dynamic binary translation. In extension to that, the structure of MuTARe is further leveraged to apply two emerging computing paradigms that can boost the power-efficiency: Near-Threshold Voltage (NTV) computing (while still supporting transparent acceleration) and Approximate Computing (AxC). Compared to a traditional heterogeneous system with DVFS support, the base MuTARe architecture can automatically improve the execution time by up to 1:3 , or adapt to the same task deadline with 1:6 smaller energy consumption, or adapt to the same low energy budget with 2:3 better performance. In NTV mode, MuTARe can transparently save further 30% energy in memory-intensive workloads by operating the combinatorial datapath at half the memory frequency. In AxC mode, MuTARe can further improve power savings by up to 50% by leveraging approximate functional units for arithmetic computations.Consumo de potência, antigamente um limitante no projeto apenas de sistemas embarcados, hoje é um dos principais objetivos de otimização em todos os domínios de dispositivos, desde a computação na núvem até a computação na borda. Aceleradores de propósito específico são capazes de fornecer uma solução para o processamento de baixa potência ao adequar o hardware à aplicação; porém, visto que, em diversos domínios, o hardware necessita executar uma ampla gama de aplicações, cada uma com diferentes requisitos computacionais, abordagens alternativas se fazem necessárias. Além disso, o mesmo hardware precisa se adequar, em tempo de execução, ao estado do sistema e tamanho da carga de trabalho, aumentando o poder computacional ao executar uma tarefa exigente e reduzindo-o quando inativo. De forma a resolver estes problemas, esta tese apresenta um acelerador de proposito geral que pode ser acoplado a um conjunto heterogeneo de cores e suporta DVFS, sinergisticamente combinando técnicas para uma melhor combinação entre diferentes aplicações e hardware quando comparado aos designs existentes hoje. A arquitetura resultante, MuTARe, provê uma estrutura regular e reconfigurável que é adequada para aceleração automática de código já exisente através de tradução binária. Além disso, MuTARe também provê uma estrutura adequada para aplicar dois emergentes paradigmas de computação que podem aumentar a eficiencia de potência: computação no nível da tensão de threshold (mantendo a capacidade de aceleração transparente) e computação aproximativa. Comparado a um sistema heterogeneo tradicional com suporte a DVFS, a arquitetura MuTARe base pode automaticamente melhorar o tempo de execução em 1:3 , ou adaptar-se para o mesmo baixo tempo de execução com uma redução de 1:6 no consumo energético, ou adaptar-se para o mesmo baixo nível de energia com 2:3 melhor performance. No modo near-threshold, MuTARe pode melhorar o consumo de potência de forma transparente em mais 30% em tarefas que exigem bastante memória operando o circuito combinacional à metade da frequencia da memória. No modo computação aproximativa, MuTARe consegue melhorar o consumo de potência em até mais 50% usando unidades funcionais aproximativas para as computações.application/pdfengArquiteturas reconfiguraveisComputação aproximativaComputer architectureReconfigurable architectureAdaptable architectureMuTARe : a multi-target, adaptive reconfigurable architectureMuTARe : uma arquitetura multi-proposito adaptativa e reconfigurávelinfo:eu-repo/semantics/publishedVersioninfo:eu-repo/semantics/doctoralThesisUniversidade Federal do Rio Grande do SulInstituto de InformáticaPrograma de Pós-Graduação em ComputaçãoPorto Alegre, BR-RS2019doutoradoinfo:eu-repo/semantics/openAccessreponame:Biblioteca Digital de Teses e Dissertações da UFRGSinstname:Universidade Federal do Rio Grande do Sul (UFRGS)instacron:UFRGSTEXT001093309.pdf.txt001093309.pdf.txtExtracted Texttext/plain293321http://www.lume.ufrgs.br/bitstream/10183/212551/2/001093309.pdf.txtbf7acf1899c1b4939051454ce4b5efbeMD52ORIGINAL001093309.pdfTexto completo (inglês)application/pdf6387719http://www.lume.ufrgs.br/bitstream/10183/212551/1/001093309.pdf669474bfa126221e5adfdc9052963310MD5110183/2125512020-08-05 03:39:04.447975oai:www.lume.ufrgs.br:10183/212551Biblioteca Digital de Teses e Dissertaçõeshttps://lume.ufrgs.br/handle/10183/2PUBhttps://lume.ufrgs.br/oai/requestlume@ufrgs.br||lume@ufrgs.bropendoar:18532020-08-05T06:39:04Biblioteca Digital de Teses e Dissertações da UFRGS - Universidade Federal do Rio Grande do Sul (UFRGS)false
dc.title.pt_BR.fl_str_mv MuTARe : a multi-target, adaptive reconfigurable architecture
dc.title.alternative.pt.fl_str_mv MuTARe : uma arquitetura multi-proposito adaptativa e reconfigurável
title MuTARe : a multi-target, adaptive reconfigurable architecture
spellingShingle MuTARe : a multi-target, adaptive reconfigurable architecture
Brandalero, Marcelo
Arquiteturas reconfiguraveis
Computação aproximativa
Computer architecture
Reconfigurable architecture
Adaptable architecture
title_short MuTARe : a multi-target, adaptive reconfigurable architecture
title_full MuTARe : a multi-target, adaptive reconfigurable architecture
title_fullStr MuTARe : a multi-target, adaptive reconfigurable architecture
title_full_unstemmed MuTARe : a multi-target, adaptive reconfigurable architecture
title_sort MuTARe : a multi-target, adaptive reconfigurable architecture
author Brandalero, Marcelo
author_facet Brandalero, Marcelo
author_role author
dc.contributor.author.fl_str_mv Brandalero, Marcelo
dc.contributor.advisor1.fl_str_mv Beck Filho, Antonio Carlos Schneider
dc.contributor.advisor-co1.fl_str_mv Carro, Luigi
contributor_str_mv Beck Filho, Antonio Carlos Schneider
Carro, Luigi
dc.subject.por.fl_str_mv Arquiteturas reconfiguraveis
Computação aproximativa
topic Arquiteturas reconfiguraveis
Computação aproximativa
Computer architecture
Reconfigurable architecture
Adaptable architecture
dc.subject.eng.fl_str_mv Computer architecture
Reconfigurable architecture
Adaptable architecture
description Power consumption, earlier a design constraint only in embedded systems, has become the major driver for architectural optimizations in all domains, from the cloud to the edge. Application-specific accelerators provide a low-power processing solution by efficiently matching the hardware to the application; however, since in many domains the hardware must execute efficiently a broad range of fast-evolving applications, unpredictable at design time and each with distinct resource requirements, alternatives approaches are required. Besides that, the same hardware must also adapt the computational power at run time to the system status and workload sizes. To address these issues, this thesis presents a general-purpose reconfigurable accelerator that can be coupled to a heterogeneous set of cores and supports Dynamic Voltage and Frequency Scaling (DVFS), synergistically combining the techniques for a better match between different applications and hardware when compared to current designs. The resulting architecture, MuTARe, provides a coarse-grained regular and reconfigurable structure which is suitable for automatic acceleration of deployed code through dynamic binary translation. In extension to that, the structure of MuTARe is further leveraged to apply two emerging computing paradigms that can boost the power-efficiency: Near-Threshold Voltage (NTV) computing (while still supporting transparent acceleration) and Approximate Computing (AxC). Compared to a traditional heterogeneous system with DVFS support, the base MuTARe architecture can automatically improve the execution time by up to 1:3 , or adapt to the same task deadline with 1:6 smaller energy consumption, or adapt to the same low energy budget with 2:3 better performance. In NTV mode, MuTARe can transparently save further 30% energy in memory-intensive workloads by operating the combinatorial datapath at half the memory frequency. In AxC mode, MuTARe can further improve power savings by up to 50% by leveraging approximate functional units for arithmetic computations.
publishDate 2019
dc.date.issued.fl_str_mv 2019
dc.date.accessioned.fl_str_mv 2020-08-01T03:59:43Z
dc.type.status.fl_str_mv info:eu-repo/semantics/publishedVersion
dc.type.driver.fl_str_mv info:eu-repo/semantics/doctoralThesis
format doctoralThesis
status_str publishedVersion
dc.identifier.uri.fl_str_mv http://hdl.handle.net/10183/212551
dc.identifier.nrb.pt_BR.fl_str_mv 001093309
url http://hdl.handle.net/10183/212551
identifier_str_mv 001093309
dc.language.iso.fl_str_mv eng
language eng
dc.rights.driver.fl_str_mv info:eu-repo/semantics/openAccess
eu_rights_str_mv openAccess
dc.format.none.fl_str_mv application/pdf
dc.source.none.fl_str_mv reponame:Biblioteca Digital de Teses e Dissertações da UFRGS
instname:Universidade Federal do Rio Grande do Sul (UFRGS)
instacron:UFRGS
instname_str Universidade Federal do Rio Grande do Sul (UFRGS)
instacron_str UFRGS
institution UFRGS
reponame_str Biblioteca Digital de Teses e Dissertações da UFRGS
collection Biblioteca Digital de Teses e Dissertações da UFRGS
bitstream.url.fl_str_mv http://www.lume.ufrgs.br/bitstream/10183/212551/2/001093309.pdf.txt
http://www.lume.ufrgs.br/bitstream/10183/212551/1/001093309.pdf
bitstream.checksum.fl_str_mv bf7acf1899c1b4939051454ce4b5efbe
669474bfa126221e5adfdc9052963310
bitstream.checksumAlgorithm.fl_str_mv MD5
MD5
repository.name.fl_str_mv Biblioteca Digital de Teses e Dissertações da UFRGS - Universidade Federal do Rio Grande do Sul (UFRGS)
repository.mail.fl_str_mv lume@ufrgs.br||lume@ufrgs.br
_version_ 1800309167952494592