DRAFT: An On-line Fault Detection Method for Dynamic and Partially Reconfigurable FPGAs

• Autor(a) principal: Manuel Gericota
• Data de Publicação: 2001
• Outros Autores: Gustavo Costa Alves, Miguel L. Silva, José Martins Ferreira
• Tipo de documento: Livro
• Idioma: eng
• Título da fonte: Repositório Científico de Acesso Aberto de Portugal (Repositórios Cientìficos)
• Texto Completo: https://hdl.handle.net/10216/85045
• topic: Engenharia electrotécnica, Ciências da educação; Electrical engineering, Educational sciences

Reconfigurable systems have benefited of the novel partial dynamic reconfiguration features of recent FPGA devices. Enabling the concurrent reconfiguration without disturbing system operation, this technology has raised a new test challenge: to assure a continuously fault-free operation, independently of the circuit present after many reconfiguration processes, testing the FPGA without disturbing the whole system operation. Re-using the IEEE 1149.1 infrastructure, already widely used for In-System Programming, and exploiting the same dynamic and partially reconfigurable features underlying this test challenge, this paper develops a new structural concurrent test approach able to detect faults and introduce fault tolerance features, without disturbing system operation, in the field and throughout its lifetime.