DRAFT: An On-line Concurrent Test for Partial and Dynamically Reconfigurable FPGAs

Detalhes bibliográficos
Autor(a) principal: Manuel Gericota
Data de Publicação: 2001
Outros Autores: Gustavo Costa Alves, Miguel L. Silva, José Martins Ferreira
Tipo de documento: Livro
Idioma: eng
Título da fonte: Repositório Científico de Acesso Aberto de Portugal (Repositórios Cientìficos)
Texto Completo: https://hdl.handle.net/10216/85053
Resumo: The use of partial and dynamically reconfigurable FPGAs in reconfigurable systems opens exciting possibilities, since they enable the concurrent reconfiguration of part of the system without interrupting its operation. Nevertheless, larger dies and the use of smaller submicron scales in the manufacturing of this new kind of FPGAs increase the probability of failures after many reconfiguration processes. New methods of test and fault tolerance are therefore required, capable of ensuring system reliability. This paper presents improvements to our RaT Freed Resources technique, a structural concurrent test approach able to detect and diagnose faults without disturbing system operation, throughout its lifetime.
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spelling DRAFT: An On-line Concurrent Test for Partial and Dynamically Reconfigurable FPGAsEngenharia electrotécnica, Engenharia electrotécnica, electrónica e informáticaElectrical engineering, Electrical engineering, Electronic engineering, Information engineeringThe use of partial and dynamically reconfigurable FPGAs in reconfigurable systems opens exciting possibilities, since they enable the concurrent reconfiguration of part of the system without interrupting its operation. Nevertheless, larger dies and the use of smaller submicron scales in the manufacturing of this new kind of FPGAs increase the probability of failures after many reconfiguration processes. New methods of test and fault tolerance are therefore required, capable of ensuring system reliability. This paper presents improvements to our RaT Freed Resources technique, a structural concurrent test approach able to detect and diagnose faults without disturbing system operation, throughout its lifetime.20012001-01-01T00:00:00Zinfo:eu-repo/semantics/publishedVersioninfo:eu-repo/semantics/bookapplication/pdfhttps://hdl.handle.net/10216/85053engManuel GericotaGustavo Costa AlvesMiguel L. SilvaJosé Martins Ferreirainfo:eu-repo/semantics/openAccessreponame:Repositório Científico de Acesso Aberto de Portugal (Repositórios Cientìficos)instname:Agência para a Sociedade do Conhecimento (UMIC) - FCT - Sociedade da Informaçãoinstacron:RCAAP2023-11-29T13:10:33Zoai:repositorio-aberto.up.pt:10216/85053Portal AgregadorONGhttps://www.rcaap.pt/oai/openaireopendoar:71602024-03-19T23:35:06.410382Repositório Científico de Acesso Aberto de Portugal (Repositórios Cientìficos) - Agência para a Sociedade do Conhecimento (UMIC) - FCT - Sociedade da Informaçãofalse
dc.title.none.fl_str_mv DRAFT: An On-line Concurrent Test for Partial and Dynamically Reconfigurable FPGAs
title DRAFT: An On-line Concurrent Test for Partial and Dynamically Reconfigurable FPGAs
spellingShingle DRAFT: An On-line Concurrent Test for Partial and Dynamically Reconfigurable FPGAs
Manuel Gericota
Engenharia electrotécnica, Engenharia electrotécnica, electrónica e informática
Electrical engineering, Electrical engineering, Electronic engineering, Information engineering
title_short DRAFT: An On-line Concurrent Test for Partial and Dynamically Reconfigurable FPGAs
title_full DRAFT: An On-line Concurrent Test for Partial and Dynamically Reconfigurable FPGAs
title_fullStr DRAFT: An On-line Concurrent Test for Partial and Dynamically Reconfigurable FPGAs
title_full_unstemmed DRAFT: An On-line Concurrent Test for Partial and Dynamically Reconfigurable FPGAs
title_sort DRAFT: An On-line Concurrent Test for Partial and Dynamically Reconfigurable FPGAs
author Manuel Gericota
author_facet Manuel Gericota
Gustavo Costa Alves
Miguel L. Silva
José Martins Ferreira
author_role author
author2 Gustavo Costa Alves
Miguel L. Silva
José Martins Ferreira
author2_role author
author
author
dc.contributor.author.fl_str_mv Manuel Gericota
Gustavo Costa Alves
Miguel L. Silva
José Martins Ferreira
dc.subject.por.fl_str_mv Engenharia electrotécnica, Engenharia electrotécnica, electrónica e informática
Electrical engineering, Electrical engineering, Electronic engineering, Information engineering
topic Engenharia electrotécnica, Engenharia electrotécnica, electrónica e informática
Electrical engineering, Electrical engineering, Electronic engineering, Information engineering
description The use of partial and dynamically reconfigurable FPGAs in reconfigurable systems opens exciting possibilities, since they enable the concurrent reconfiguration of part of the system without interrupting its operation. Nevertheless, larger dies and the use of smaller submicron scales in the manufacturing of this new kind of FPGAs increase the probability of failures after many reconfiguration processes. New methods of test and fault tolerance are therefore required, capable of ensuring system reliability. This paper presents improvements to our RaT Freed Resources technique, a structural concurrent test approach able to detect and diagnose faults without disturbing system operation, throughout its lifetime.
publishDate 2001
dc.date.none.fl_str_mv 2001
2001-01-01T00:00:00Z
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dc.type.driver.fl_str_mv info:eu-repo/semantics/book
format book
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dc.identifier.uri.fl_str_mv https://hdl.handle.net/10216/85053
url https://hdl.handle.net/10216/85053
dc.language.iso.fl_str_mv eng
language eng
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repository.name.fl_str_mv Repositório Científico de Acesso Aberto de Portugal (Repositórios Cientìficos) - Agência para a Sociedade do Conhecimento (UMIC) - FCT - Sociedade da Informação
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