Configurable M-factor VLSI DVB-S2 LDPC decoder architecture with optimized memory tiling design
Autor(a) principal: | |
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Data de Publicação: | 2012 |
Outros Autores: | , , , |
Tipo de documento: | Artigo |
Idioma: | eng |
Título da fonte: | Repositório Científico de Acesso Aberto de Portugal (Repositórios Cientìficos) |
Texto Completo: | http://hdl.handle.net/10316/102728 https://doi.org/10.1186/1687-1499-2012-98 |
Resumo: | Semi-parallel architectures for decoding Digital Video Broadcasting-Satellite 2 (DVB-S2) Low-Density Parity-Check (LDPC) codes have improved Very Large Scale Integration (VLSI) solutions, but their design is challenging from several perspectives. In order to conveniently exploit parallelism for obtaining VLSI LDPC decoders that occupy small circuit areas and demand low power consumption, we propose in this article a novel ASIC reconfigurable approach that exploits efficiently the memory block reshaping required to use a reduced number of processor nodes. We exploit different memory tiling configurations to reduce the memory area about 20%. The proposed architecture was synthesized for a 90 nm process design with a variable number of processor nodes and a competitive circuit area of 6.2 mm2 was achieved. The operating frequency simultaneously guarantees throughputs superior to 90 Mbps, as required by DVB-S2, and low levels of power consumption |
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Repositório Científico de Acesso Aberto de Portugal (Repositórios Cientìficos) |
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7160 |
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Configurable M-factor VLSI DVB-S2 LDPC decoder architecture with optimized memory tiling designLDPC decodingDVB-S2VLSIASICmemory tilingsemi-parallel architectureM-factorizable architectureLow-power consumptionhigh-throughputSemi-parallel architectures for decoding Digital Video Broadcasting-Satellite 2 (DVB-S2) Low-Density Parity-Check (LDPC) codes have improved Very Large Scale Integration (VLSI) solutions, but their design is challenging from several perspectives. In order to conveniently exploit parallelism for obtaining VLSI LDPC decoders that occupy small circuit areas and demand low power consumption, we propose in this article a novel ASIC reconfigurable approach that exploits efficiently the memory block reshaping required to use a reduced number of processor nodes. We exploit different memory tiling configurations to reduce the memory area about 20%. The proposed architecture was synthesized for a 90 nm process design with a variable number of processor nodes and a competitive circuit area of 6.2 mm2 was achieved. The operating frequency simultaneously guarantees throughputs superior to 90 Mbps, as required by DVB-S2, and low levels of power consumption2012info:eu-repo/semantics/publishedVersioninfo:eu-repo/semantics/articlehttp://hdl.handle.net/10316/102728http://hdl.handle.net/10316/102728https://doi.org/10.1186/1687-1499-2012-98eng1687-1499Falcao, GabrielGomes, MarcoSilva, VítorSousa, LeonelCacheira, Joãoinfo:eu-repo/semantics/openAccessreponame:Repositório Científico de Acesso Aberto de Portugal (Repositórios Cientìficos)instname:Agência para a Sociedade do Conhecimento (UMIC) - FCT - Sociedade da Informaçãoinstacron:RCAAP2022-10-10T20:31:37Zoai:estudogeral.uc.pt:10316/102728Portal AgregadorONGhttps://www.rcaap.pt/oai/openaireopendoar:71602024-03-19T21:19:39.757399Repositório Científico de Acesso Aberto de Portugal (Repositórios Cientìficos) - Agência para a Sociedade do Conhecimento (UMIC) - FCT - Sociedade da Informaçãofalse |
dc.title.none.fl_str_mv |
Configurable M-factor VLSI DVB-S2 LDPC decoder architecture with optimized memory tiling design |
title |
Configurable M-factor VLSI DVB-S2 LDPC decoder architecture with optimized memory tiling design |
spellingShingle |
Configurable M-factor VLSI DVB-S2 LDPC decoder architecture with optimized memory tiling design Falcao, Gabriel LDPC decoding DVB-S2 VLSI ASIC memory tiling semi-parallel architecture M-factorizable architecture Low-power consumption high-throughput |
title_short |
Configurable M-factor VLSI DVB-S2 LDPC decoder architecture with optimized memory tiling design |
title_full |
Configurable M-factor VLSI DVB-S2 LDPC decoder architecture with optimized memory tiling design |
title_fullStr |
Configurable M-factor VLSI DVB-S2 LDPC decoder architecture with optimized memory tiling design |
title_full_unstemmed |
Configurable M-factor VLSI DVB-S2 LDPC decoder architecture with optimized memory tiling design |
title_sort |
Configurable M-factor VLSI DVB-S2 LDPC decoder architecture with optimized memory tiling design |
author |
Falcao, Gabriel |
author_facet |
Falcao, Gabriel Gomes, Marco Silva, Vítor Sousa, Leonel Cacheira, João |
author_role |
author |
author2 |
Gomes, Marco Silva, Vítor Sousa, Leonel Cacheira, João |
author2_role |
author author author author |
dc.contributor.author.fl_str_mv |
Falcao, Gabriel Gomes, Marco Silva, Vítor Sousa, Leonel Cacheira, João |
dc.subject.por.fl_str_mv |
LDPC decoding DVB-S2 VLSI ASIC memory tiling semi-parallel architecture M-factorizable architecture Low-power consumption high-throughput |
topic |
LDPC decoding DVB-S2 VLSI ASIC memory tiling semi-parallel architecture M-factorizable architecture Low-power consumption high-throughput |
description |
Semi-parallel architectures for decoding Digital Video Broadcasting-Satellite 2 (DVB-S2) Low-Density Parity-Check (LDPC) codes have improved Very Large Scale Integration (VLSI) solutions, but their design is challenging from several perspectives. In order to conveniently exploit parallelism for obtaining VLSI LDPC decoders that occupy small circuit areas and demand low power consumption, we propose in this article a novel ASIC reconfigurable approach that exploits efficiently the memory block reshaping required to use a reduced number of processor nodes. We exploit different memory tiling configurations to reduce the memory area about 20%. The proposed architecture was synthesized for a 90 nm process design with a variable number of processor nodes and a competitive circuit area of 6.2 mm2 was achieved. The operating frequency simultaneously guarantees throughputs superior to 90 Mbps, as required by DVB-S2, and low levels of power consumption |
publishDate |
2012 |
dc.date.none.fl_str_mv |
2012 |
dc.type.status.fl_str_mv |
info:eu-repo/semantics/publishedVersion |
dc.type.driver.fl_str_mv |
info:eu-repo/semantics/article |
format |
article |
status_str |
publishedVersion |
dc.identifier.uri.fl_str_mv |
http://hdl.handle.net/10316/102728 http://hdl.handle.net/10316/102728 https://doi.org/10.1186/1687-1499-2012-98 |
url |
http://hdl.handle.net/10316/102728 https://doi.org/10.1186/1687-1499-2012-98 |
dc.language.iso.fl_str_mv |
eng |
language |
eng |
dc.relation.none.fl_str_mv |
1687-1499 |
dc.rights.driver.fl_str_mv |
info:eu-repo/semantics/openAccess |
eu_rights_str_mv |
openAccess |
dc.source.none.fl_str_mv |
reponame:Repositório Científico de Acesso Aberto de Portugal (Repositórios Cientìficos) instname:Agência para a Sociedade do Conhecimento (UMIC) - FCT - Sociedade da Informação instacron:RCAAP |
instname_str |
Agência para a Sociedade do Conhecimento (UMIC) - FCT - Sociedade da Informação |
instacron_str |
RCAAP |
institution |
RCAAP |
reponame_str |
Repositório Científico de Acesso Aberto de Portugal (Repositórios Cientìficos) |
collection |
Repositório Científico de Acesso Aberto de Portugal (Repositórios Cientìficos) |
repository.name.fl_str_mv |
Repositório Científico de Acesso Aberto de Portugal (Repositórios Cientìficos) - Agência para a Sociedade do Conhecimento (UMIC) - FCT - Sociedade da Informação |
repository.mail.fl_str_mv |
|
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1799134090698424320 |