HDL approach to board-level BIST

Detalhes bibliográficos
Autor(a) principal: Gustavo R. Alves
Data de Publicação: 1993
Outros Autores: Manuel G. Gericota, José L. Ramalho, José M. M. Ferreira
Tipo de documento: Livro
Idioma: eng
Título da fonte: Repositório Científico de Acesso Aberto de Portugal (Repositórios Cientìficos)
Texto Completo: https://repositorio-aberto.up.pt/handle/10216/84553
Resumo: Boundary scan is now the most promising technology for testing high-complexity printed circuit boards. The number of BST components available to board-level designers is however still restricted, limiting the achievable fault coverage. The requirements to improve board-level testability are analyzed, and a corresponding set of testability building blocks are proposed. A high flexibility and reduced cost solution is described, which implements these blocks on medium-complexity PLDs using a simple and powerful HDL.
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spelling HDL approach to board-level BISTEngenharia electrotécnica, Engenharia electrotécnica, electrónica e informáticaElectrical engineering, Electrical engineering, Electronic engineering, Information engineeringBoundary scan is now the most promising technology for testing high-complexity printed circuit boards. The number of BST components available to board-level designers is however still restricted, limiting the achievable fault coverage. The requirements to improve board-level testability are analyzed, and a corresponding set of testability building blocks are proposed. A high flexibility and reduced cost solution is described, which implements these blocks on medium-complexity PLDs using a simple and powerful HDL.19931993-01-01T00:00:00Zinfo:eu-repo/semantics/publishedVersioninfo:eu-repo/semantics/bookapplication/pdfhttps://repositorio-aberto.up.pt/handle/10216/84553eng10.1109/EURDAC.1993.410669Gustavo R. AlvesManuel G. GericotaJosé L. RamalhoJosé M. M. Ferreirainfo:eu-repo/semantics/openAccessreponame:Repositório Científico de Acesso Aberto de Portugal (Repositórios Cientìficos)instname:Agência para a Sociedade do Conhecimento (UMIC) - FCT - Sociedade da Informaçãoinstacron:RCAAP2023-11-29T15:33:07Zoai:repositorio-aberto.up.pt:10216/84553Portal AgregadorONGhttps://www.rcaap.pt/oai/openaireopendoar:71602024-03-20T00:26:24.198545Repositório Científico de Acesso Aberto de Portugal (Repositórios Cientìficos) - Agência para a Sociedade do Conhecimento (UMIC) - FCT - Sociedade da Informaçãofalse
dc.title.none.fl_str_mv HDL approach to board-level BIST
title HDL approach to board-level BIST
spellingShingle HDL approach to board-level BIST
Gustavo R. Alves
Engenharia electrotécnica, Engenharia electrotécnica, electrónica e informática
Electrical engineering, Electrical engineering, Electronic engineering, Information engineering
title_short HDL approach to board-level BIST
title_full HDL approach to board-level BIST
title_fullStr HDL approach to board-level BIST
title_full_unstemmed HDL approach to board-level BIST
title_sort HDL approach to board-level BIST
author Gustavo R. Alves
author_facet Gustavo R. Alves
Manuel G. Gericota
José L. Ramalho
José M. M. Ferreira
author_role author
author2 Manuel G. Gericota
José L. Ramalho
José M. M. Ferreira
author2_role author
author
author
dc.contributor.author.fl_str_mv Gustavo R. Alves
Manuel G. Gericota
José L. Ramalho
José M. M. Ferreira
dc.subject.por.fl_str_mv Engenharia electrotécnica, Engenharia electrotécnica, electrónica e informática
Electrical engineering, Electrical engineering, Electronic engineering, Information engineering
topic Engenharia electrotécnica, Engenharia electrotécnica, electrónica e informática
Electrical engineering, Electrical engineering, Electronic engineering, Information engineering
description Boundary scan is now the most promising technology for testing high-complexity printed circuit boards. The number of BST components available to board-level designers is however still restricted, limiting the achievable fault coverage. The requirements to improve board-level testability are analyzed, and a corresponding set of testability building blocks are proposed. A high flexibility and reduced cost solution is described, which implements these blocks on medium-complexity PLDs using a simple and powerful HDL.
publishDate 1993
dc.date.none.fl_str_mv 1993
1993-01-01T00:00:00Z
dc.type.status.fl_str_mv info:eu-repo/semantics/publishedVersion
dc.type.driver.fl_str_mv info:eu-repo/semantics/book
format book
status_str publishedVersion
dc.identifier.uri.fl_str_mv https://repositorio-aberto.up.pt/handle/10216/84553
url https://repositorio-aberto.up.pt/handle/10216/84553
dc.language.iso.fl_str_mv eng
language eng
dc.relation.none.fl_str_mv 10.1109/EURDAC.1993.410669
dc.rights.driver.fl_str_mv info:eu-repo/semantics/openAccess
eu_rights_str_mv openAccess
dc.format.none.fl_str_mv application/pdf
dc.source.none.fl_str_mv reponame:Repositório Científico de Acesso Aberto de Portugal (Repositórios Cientìficos)
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instname_str Agência para a Sociedade do Conhecimento (UMIC) - FCT - Sociedade da Informação
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collection Repositório Científico de Acesso Aberto de Portugal (Repositórios Cientìficos)
repository.name.fl_str_mv Repositório Científico de Acesso Aberto de Portugal (Repositórios Cientìficos) - Agência para a Sociedade do Conhecimento (UMIC) - FCT - Sociedade da Informação
repository.mail.fl_str_mv
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