DRAFT: A scanning test methodology for dynamic and partially reconfigurable FPGAs

Detalhes bibliográficos
Autor(a) principal: Manuel G. Gericota
Data de Publicação: 2001
Outros Autores: Gustavo R. Alves, Miguel L. Silva, José M. Ferreira
Tipo de documento: Livro
Idioma: eng
Título da fonte: Repositório Científico de Acesso Aberto de Portugal (Repositórios Cientìficos)
Texto Completo: https://hdl.handle.net/10216/85022
Resumo: A new class of FPGAs that enable partial and dynamic reconfiguration without disturbing system operation, raised a new test challenge: how to assure a continuously fault-free operation, independently of the circuit present after many reconfiguration processes. A new on-line test method for those FPGAs is proposed, based on a scanning methodology and in the reuse of the IEEE 1149.1 Boundary Scan test infrastructure, already widely employed for In-System Programming.
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spelling DRAFT: A scanning test methodology for dynamic and partially reconfigurable FPGAsEngenharia electrotécnica, Engenharia electrotécnica, electrónica e informáticaElectrical engineering, Electrical engineering, Electronic engineering, Information engineeringA new class of FPGAs that enable partial and dynamic reconfiguration without disturbing system operation, raised a new test challenge: how to assure a continuously fault-free operation, independently of the circuit present after many reconfiguration processes. A new on-line test method for those FPGAs is proposed, based on a scanning methodology and in the reuse of the IEEE 1149.1 Boundary Scan test infrastructure, already widely employed for In-System Programming.20012001-01-01T00:00:00Zinfo:eu-repo/semantics/publishedVersioninfo:eu-repo/semantics/bookapplication/pdfhttps://hdl.handle.net/10216/85022engManuel G. GericotaGustavo R. AlvesMiguel L. SilvaJosé M. Ferreirainfo:eu-repo/semantics/openAccessreponame:Repositório Científico de Acesso Aberto de Portugal (Repositórios Cientìficos)instname:Agência para a Sociedade do Conhecimento (UMIC) - FCT - Sociedade da Informaçãoinstacron:RCAAP2023-11-29T13:25:27Zoai:repositorio-aberto.up.pt:10216/85022Portal AgregadorONGhttps://www.rcaap.pt/oai/openaireopendoar:71602024-03-19T23:40:07.206931Repositório Científico de Acesso Aberto de Portugal (Repositórios Cientìficos) - Agência para a Sociedade do Conhecimento (UMIC) - FCT - Sociedade da Informaçãofalse
dc.title.none.fl_str_mv DRAFT: A scanning test methodology for dynamic and partially reconfigurable FPGAs
title DRAFT: A scanning test methodology for dynamic and partially reconfigurable FPGAs
spellingShingle DRAFT: A scanning test methodology for dynamic and partially reconfigurable FPGAs
Manuel G. Gericota
Engenharia electrotécnica, Engenharia electrotécnica, electrónica e informática
Electrical engineering, Electrical engineering, Electronic engineering, Information engineering
title_short DRAFT: A scanning test methodology for dynamic and partially reconfigurable FPGAs
title_full DRAFT: A scanning test methodology for dynamic and partially reconfigurable FPGAs
title_fullStr DRAFT: A scanning test methodology for dynamic and partially reconfigurable FPGAs
title_full_unstemmed DRAFT: A scanning test methodology for dynamic and partially reconfigurable FPGAs
title_sort DRAFT: A scanning test methodology for dynamic and partially reconfigurable FPGAs
author Manuel G. Gericota
author_facet Manuel G. Gericota
Gustavo R. Alves
Miguel L. Silva
José M. Ferreira
author_role author
author2 Gustavo R. Alves
Miguel L. Silva
José M. Ferreira
author2_role author
author
author
dc.contributor.author.fl_str_mv Manuel G. Gericota
Gustavo R. Alves
Miguel L. Silva
José M. Ferreira
dc.subject.por.fl_str_mv Engenharia electrotécnica, Engenharia electrotécnica, electrónica e informática
Electrical engineering, Electrical engineering, Electronic engineering, Information engineering
topic Engenharia electrotécnica, Engenharia electrotécnica, electrónica e informática
Electrical engineering, Electrical engineering, Electronic engineering, Information engineering
description A new class of FPGAs that enable partial and dynamic reconfiguration without disturbing system operation, raised a new test challenge: how to assure a continuously fault-free operation, independently of the circuit present after many reconfiguration processes. A new on-line test method for those FPGAs is proposed, based on a scanning methodology and in the reuse of the IEEE 1149.1 Boundary Scan test infrastructure, already widely employed for In-System Programming.
publishDate 2001
dc.date.none.fl_str_mv 2001
2001-01-01T00:00:00Z
dc.type.status.fl_str_mv info:eu-repo/semantics/publishedVersion
dc.type.driver.fl_str_mv info:eu-repo/semantics/book
format book
status_str publishedVersion
dc.identifier.uri.fl_str_mv https://hdl.handle.net/10216/85022
url https://hdl.handle.net/10216/85022
dc.language.iso.fl_str_mv eng
language eng
dc.rights.driver.fl_str_mv info:eu-repo/semantics/openAccess
eu_rights_str_mv openAccess
dc.format.none.fl_str_mv application/pdf
dc.source.none.fl_str_mv reponame:Repositório Científico de Acesso Aberto de Portugal (Repositórios Cientìficos)
instname:Agência para a Sociedade do Conhecimento (UMIC) - FCT - Sociedade da Informação
instacron:RCAAP
instname_str Agência para a Sociedade do Conhecimento (UMIC) - FCT - Sociedade da Informação
instacron_str RCAAP
institution RCAAP
reponame_str Repositório Científico de Acesso Aberto de Portugal (Repositórios Cientìficos)
collection Repositório Científico de Acesso Aberto de Portugal (Repositórios Cientìficos)
repository.name.fl_str_mv Repositório Científico de Acesso Aberto de Portugal (Repositórios Cientìficos) - Agência para a Sociedade do Conhecimento (UMIC) - FCT - Sociedade da Informação
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