FPGA implementation of a 5G-NR DU Rx Uplink chain

• Autor(a) principal: Coutinho, Fábio Daniel Lopes
• Data de Publicação: 2019
• Tipo de documento: Dissertação
• Idioma: eng
• Título da fonte: Repositório Científico de Acesso Aberto de Portugal (Repositórios Cientìficos)
• Texto Completo: http://hdl.handle.net/10773/29637
• topic: 5G; 5G NR; eMBB; URLLC; mMTC; RAN; OFDM; PHY; FPGA

With the constant evolution of the communication systems, the 5G is rapidly becoming a necessity and a reality. In this sense, three scenarios were established, Enhanced Mobile Broadband (eMBB), Ultra Reliable Low Latency Communications (URLLC) and massive Machine Type Communications (mMTC), being this scenarios the base for the study and development of this new communication system. For that, 3GPP specify the radio access network (RAN) division, passing from the traditional eNB (Long Term Evolution) to the Central Unit (CU) and the Distributed Unit (DU) (New Radio), making it more flexible. Conventionally, the processing functions (L1,L2 and L3) are co-located in the Base Band Unit (BBU), making the data rates in the fronthaul too high for 5G scenarios. This dissertation focus on the Uplink chain implementation of the 5th Generation NR DU, being that the DU will be composed by processing functions from the BBU, more concretely by a reception chain of the Cyclic Prefix Orthogonal Frequency Division Multiplexing (split 7.1), in order to decrease the data rates in the fronthaul. For that, a previous study about the physical layer (PHY) and the synchronization procedures was done, followed by the Matlab implementation. For reception chain implementation, a tool used that synthesizes Simulink models in VHSIC Hardware Description Language (VHDL) code, the HDL Coder. After testbench simulation, it was performed the validation in the Field Programmable Gate Array (FPGA).