FPGA implementation of a 5G-NR DU Rx Uplink chain
Autor(a) principal: | |
---|---|
Data de Publicação: | 2019 |
Tipo de documento: | Dissertação |
Idioma: | eng |
Título da fonte: | Repositório Científico de Acesso Aberto de Portugal (Repositórios Cientìficos) |
Texto Completo: | http://hdl.handle.net/10773/29637 |
Resumo: | With the constant evolution of the communication systems, the 5G is rapidly becoming a necessity and a reality. In this sense, three scenarios were established, Enhanced Mobile Broadband (eMBB), Ultra Reliable Low Latency Communications (URLLC) and massive Machine Type Communications (mMTC), being this scenarios the base for the study and development of this new communication system. For that, 3GPP specify the radio access network (RAN) division, passing from the traditional eNB (Long Term Evolution) to the Central Unit (CU) and the Distributed Unit (DU) (New Radio), making it more flexible. Conventionally, the processing functions (L1,L2 and L3) are co-located in the Base Band Unit (BBU), making the data rates in the fronthaul too high for 5G scenarios. This dissertation focus on the Uplink chain implementation of the 5th Generation NR DU, being that the DU will be composed by processing functions from the BBU, more concretely by a reception chain of the Cyclic Prefix Orthogonal Frequency Division Multiplexing (split 7.1), in order to decrease the data rates in the fronthaul. For that, a previous study about the physical layer (PHY) and the synchronization procedures was done, followed by the Matlab implementation. For reception chain implementation, a tool used that synthesizes Simulink models in VHSIC Hardware Description Language (VHDL) code, the HDL Coder. After testbench simulation, it was performed the validation in the Field Programmable Gate Array (FPGA). |
id |
RCAP_50268bea4cbbee981cda814949f91da2 |
---|---|
oai_identifier_str |
oai:ria.ua.pt:10773/29637 |
network_acronym_str |
RCAP |
network_name_str |
Repositório Científico de Acesso Aberto de Portugal (Repositórios Cientìficos) |
repository_id_str |
7160 |
spelling |
FPGA implementation of a 5G-NR DU Rx Uplink chain5G5G NReMBBURLLCmMTCRANOFDMPHYFPGAWith the constant evolution of the communication systems, the 5G is rapidly becoming a necessity and a reality. In this sense, three scenarios were established, Enhanced Mobile Broadband (eMBB), Ultra Reliable Low Latency Communications (URLLC) and massive Machine Type Communications (mMTC), being this scenarios the base for the study and development of this new communication system. For that, 3GPP specify the radio access network (RAN) division, passing from the traditional eNB (Long Term Evolution) to the Central Unit (CU) and the Distributed Unit (DU) (New Radio), making it more flexible. Conventionally, the processing functions (L1,L2 and L3) are co-located in the Base Band Unit (BBU), making the data rates in the fronthaul too high for 5G scenarios. This dissertation focus on the Uplink chain implementation of the 5th Generation NR DU, being that the DU will be composed by processing functions from the BBU, more concretely by a reception chain of the Cyclic Prefix Orthogonal Frequency Division Multiplexing (split 7.1), in order to decrease the data rates in the fronthaul. For that, a previous study about the physical layer (PHY) and the synchronization procedures was done, followed by the Matlab implementation. For reception chain implementation, a tool used that synthesizes Simulink models in VHSIC Hardware Description Language (VHDL) code, the HDL Coder. After testbench simulation, it was performed the validation in the Field Programmable Gate Array (FPGA).Com a constante evolução dos sistemas de comunicação, o 5G está rapidamente a tornar-se numa necessidade e uma realidade. Nesse sentido, três cenários de comunicação foram estabelecidos, Enhanced Mobile Broadband (eMBB), Ultra Reliable Low Latency Communications (URLLC) e massive Machine Type Communications (mMTC), sendo a base do estudo e desenvolvimento deste novo sistema de comunicação. Para tal, a 3GPP especificou a divisão da arquitetura rádio de acesso à rede (RAN), passando do tradicional eNB (Long Term Evolution) para Central Unit (CU) e Distributed Unit (DU) (New Radio), tornando-a assim mais flexível. Convencionalmente, as funções de processamento (L1, L2 e L3) estão co-localizadas na Base Band Unit (BBU), fazendo com que as taxas de transferências no fronthaul sejam demasiado elevadas para cenários 5G. Esta dissertação foca-se na implementação da cadeia de receção Uplink de uma DU 5th Generation NR, sendo que a DU será composta por funções de processamento provenientes da BBU, mais concretamente por uma cadeia de receção Cyclic Prefix Orthogonal Frequency Division Multiplexing (split 7.1), de modo a obter taxas de transferência mais baixas no fronthaul. Para tal, um estudo prévio sobre a camada física (PHY) foi realizado assim como os procedimentos de sincronização, seguidos da modulação em Matlab. Para implementação da cadeia de receção, foi usada uma ferramenta que sintetiza modelos Simulink em código VHSIC Hardware Description Language (VHDL), o HDL Coder. Após simulação em testbench, foi feita a validação numa Field Programmable Gate Array (FPGA).2020-10-29T15:50:03Z2019-07-01T00:00:00Z2019-07info:eu-repo/semantics/publishedVersioninfo:eu-repo/semantics/masterThesisapplication/pdfhttp://hdl.handle.net/10773/29637engCoutinho, Fábio Daniel Lopesinfo:eu-repo/semantics/openAccessreponame:Repositório Científico de Acesso Aberto de Portugal (Repositórios Cientìficos)instname:Agência para a Sociedade do Conhecimento (UMIC) - FCT - Sociedade da Informaçãoinstacron:RCAAP2024-02-22T11:57:21Zoai:ria.ua.pt:10773/29637Portal AgregadorONGhttps://www.rcaap.pt/oai/openaireopendoar:71602024-03-20T03:01:55.334245Repositório Científico de Acesso Aberto de Portugal (Repositórios Cientìficos) - Agência para a Sociedade do Conhecimento (UMIC) - FCT - Sociedade da Informaçãofalse |
dc.title.none.fl_str_mv |
FPGA implementation of a 5G-NR DU Rx Uplink chain |
title |
FPGA implementation of a 5G-NR DU Rx Uplink chain |
spellingShingle |
FPGA implementation of a 5G-NR DU Rx Uplink chain Coutinho, Fábio Daniel Lopes 5G 5G NR eMBB URLLC mMTC RAN OFDM PHY FPGA |
title_short |
FPGA implementation of a 5G-NR DU Rx Uplink chain |
title_full |
FPGA implementation of a 5G-NR DU Rx Uplink chain |
title_fullStr |
FPGA implementation of a 5G-NR DU Rx Uplink chain |
title_full_unstemmed |
FPGA implementation of a 5G-NR DU Rx Uplink chain |
title_sort |
FPGA implementation of a 5G-NR DU Rx Uplink chain |
author |
Coutinho, Fábio Daniel Lopes |
author_facet |
Coutinho, Fábio Daniel Lopes |
author_role |
author |
dc.contributor.author.fl_str_mv |
Coutinho, Fábio Daniel Lopes |
dc.subject.por.fl_str_mv |
5G 5G NR eMBB URLLC mMTC RAN OFDM PHY FPGA |
topic |
5G 5G NR eMBB URLLC mMTC RAN OFDM PHY FPGA |
description |
With the constant evolution of the communication systems, the 5G is rapidly becoming a necessity and a reality. In this sense, three scenarios were established, Enhanced Mobile Broadband (eMBB), Ultra Reliable Low Latency Communications (URLLC) and massive Machine Type Communications (mMTC), being this scenarios the base for the study and development of this new communication system. For that, 3GPP specify the radio access network (RAN) division, passing from the traditional eNB (Long Term Evolution) to the Central Unit (CU) and the Distributed Unit (DU) (New Radio), making it more flexible. Conventionally, the processing functions (L1,L2 and L3) are co-located in the Base Band Unit (BBU), making the data rates in the fronthaul too high for 5G scenarios. This dissertation focus on the Uplink chain implementation of the 5th Generation NR DU, being that the DU will be composed by processing functions from the BBU, more concretely by a reception chain of the Cyclic Prefix Orthogonal Frequency Division Multiplexing (split 7.1), in order to decrease the data rates in the fronthaul. For that, a previous study about the physical layer (PHY) and the synchronization procedures was done, followed by the Matlab implementation. For reception chain implementation, a tool used that synthesizes Simulink models in VHSIC Hardware Description Language (VHDL) code, the HDL Coder. After testbench simulation, it was performed the validation in the Field Programmable Gate Array (FPGA). |
publishDate |
2019 |
dc.date.none.fl_str_mv |
2019-07-01T00:00:00Z 2019-07 2020-10-29T15:50:03Z |
dc.type.status.fl_str_mv |
info:eu-repo/semantics/publishedVersion |
dc.type.driver.fl_str_mv |
info:eu-repo/semantics/masterThesis |
format |
masterThesis |
status_str |
publishedVersion |
dc.identifier.uri.fl_str_mv |
http://hdl.handle.net/10773/29637 |
url |
http://hdl.handle.net/10773/29637 |
dc.language.iso.fl_str_mv |
eng |
language |
eng |
dc.rights.driver.fl_str_mv |
info:eu-repo/semantics/openAccess |
eu_rights_str_mv |
openAccess |
dc.format.none.fl_str_mv |
application/pdf |
dc.source.none.fl_str_mv |
reponame:Repositório Científico de Acesso Aberto de Portugal (Repositórios Cientìficos) instname:Agência para a Sociedade do Conhecimento (UMIC) - FCT - Sociedade da Informação instacron:RCAAP |
instname_str |
Agência para a Sociedade do Conhecimento (UMIC) - FCT - Sociedade da Informação |
instacron_str |
RCAAP |
institution |
RCAAP |
reponame_str |
Repositório Científico de Acesso Aberto de Portugal (Repositórios Cientìficos) |
collection |
Repositório Científico de Acesso Aberto de Portugal (Repositórios Cientìficos) |
repository.name.fl_str_mv |
Repositório Científico de Acesso Aberto de Portugal (Repositórios Cientìficos) - Agência para a Sociedade do Conhecimento (UMIC) - FCT - Sociedade da Informação |
repository.mail.fl_str_mv |
|
_version_ |
1799137674723852288 |