FPGA-based 5G RU O-RAN Interface

• Autor(a) principal: Serôdio, Francisco Fischer de Almeida
• Data de Publicação: 2021
• Tipo de documento: Dissertação
• Idioma: eng
• Título da fonte: Repositório Científico de Acesso Aberto de Portugal (Repositórios Cientìficos)
• Texto Completo: http://hdl.handle.net/10773/32519
• topic: O-RAN; Fronthaul; 5G; FPGA; O-RU; IQ compression; Block floating point

In order to solve the current problems related to the increase in mobile traffic and the rising costs that a telecommunications infrastructure entails, a new topology in the field of Radio Access Networks called O-RAN or Open- RAN proposed by the O-RAN Alliance, has been set to cause a new RAN paradigm shift. This new RAN architecture divides the various functions present in the RAN into various components whose interfaces are rigorously specified, thus allowing the so-called inter-modular interoperability, which ultimately translates into a drastic reduction in the RAN's CAPEX/OPEX. Of these components, the interoperability between the baseband and radio frequency processing modules - O-DU (Open-Distributed Unit) and O-RU (Open-Radio Unit) - whose connection is called fronthaul, has proved to be the most challenging, due to the various types of information needed to be conveyed. This said, this work focused on the development of an ORAN fronthaul interface based on 10 Gigabit Ethernet over optical fiber for an O-RU based on FPGA (Field Programmable Gate Array). Thus, an architecture following the O-RAN fronthaul specifications was proposed, and covering the Ethernet PHY, MAC, synchronization and packet processing features, a Xilinx IP Core implementation (O-RAN Interface IP) was used. Of the remaining blocks required to complete the interface, the VHDL conceived Compression and Decompression of IQ samples following the BFP (Block Floating Point) algorithm, stand out. Initially planned, the manner with which the interface was to be validated revolved around achieving interoperability with an O-DU. However, due to various constraints, also resulting from the present pandemic situation, it was only possible to verify the interoperability of the Downlink chain. This said, the hardware developed in this context was validated in an isolated way, which also allowed to carry out additional performance evaluating tests on the Compressor and Decompressor in a controlled environment. This way, the interface was then validated, whose interoperability proved to be complex, due to the various external dependencies required, as well as all the rigor imposed by the O-RAN specifications.