Digital signal processor for an intelligent antenna for satellite communications

• Autor(a) principal: Rodrigues, Ivo André Moreira
• Data de Publicação: 2022
• Tipo de documento: Dissertação
• Idioma: eng
• Título da fonte: Repositório Científico de Acesso Aberto de Portugal (Repositórios Cientìficos)
• Texto Completo: http://hdl.handle.net/10773/35093
• topic: Digital beamforming; True time delay; FPGA; Phase shifting

In many places around the globe a reliable connection to the Internet or other forms of communication are not a reality. The launch of Mega Low Earth orbits (Mega- LEO) satellites seeks to mitigate this problem, in providing broadband connection anywhere in the world. However, in order to make this technology widespread, it is necessary to develop an intelligent antenna capable of establishing a high-quality connection with at least one satellite. The goal of this dissertation is to implement a digital signal processor which can be used by an intelligent antenna with beamforming capabilities. The development platform is a Xilinx ZCU208 RF-SoC FPGA where the first goal is to generate and capture signals synchronously, respectively with RF-DACs and RF-ADCs. Once the RF-DACs and RF-ADCs can be synchronized and configured at runtime, the system becomes capable of performing digital beamforming. In this dissertation, two beamforming techniques are presented and described, one based on phase shifting, and the other based on true time delay (TTD) lines. The performed tests show that the approach based on these two solutions can provide a combination of a coarse and a fine control of the signal phase, in which TTD enable coarse delay adjustment, and phase shift a fine tuning. The implemented TTD lines proved to be computationally light, as these require few resources of the FPGA and have the advantage of being able to provide long delays, which may be usefull in different scenarios. Phase shifting proved to be a fine method, as it is able to adapt the phase with better accuracy. This dissertation presents in detail the development and validation of such digital signal processor.