Development in VHDL of a 4G physical layer transmitter

• Autor(a) principal: Barbosa, Bruno de Pinho
• Data de Publicação: 2021
• Tipo de documento: Dissertação
• Idioma: eng
• Título da fonte: Repositório Científico de Acesso Aberto de Portugal (Repositórios Cientìficos)
• Texto Completo: http://hdl.handle.net/10773/31214
• topic: 5G; 5G-NR; 4G; LTE; SC-FDMA; MATLAB; FPGA; Uplink

The LTE and LTE-Advanced technologies are standards to the fourth mobile generation, or 4G. The planned successor of this mobile generation is 5G, which will be based on 5G-New Radio (5G-NR) standard. The 5G technology is on an initial phase of deployment. One of its features that are essential in this initial phase is the support for 4G communications, because many of the mobile devices currently in use do not have support for 5G communications. This support is made possible if there is an implementation where 4G and 5G networks both coexist with each other. In the future, with the increasing usage of mobile devices with 5G support, there will be a gradual migration of 4G networks to 5G, releasing frequency spectrums currently reserved for 4G so that those can be occupied by 5G. The data transmissions in 4G require quite a lot of the processing capacity of all systems within the mobile network. For 5G, the data transmissions, in terms of traffic volume and speed, are larger than 4G transmissions, requiring new systems to be implemented, to allow the processing of larger quantities of data. Implementation in hardware of a 4G Uplink transmission chain, at the physical layer level PHY-Low, will allow the optimization of certain processes that a CPU could handle, reducing CPU usage and time spent on processing. The use of FPGAs makes this possible, as FPGAs can perform parallel tasks simultaneously and perform digital signal processing. The purpose of this dissertation is the modelling of a 4G LTE Uplink transmitter, at the physical layer level. Then, synthesizable VHDL code is generated from the modeled system, which can be eventually implemented in FPGAs. The modelling of the system is made in Simulink, a tool inside the MATLAB software, which allows for modelling, simulating and analyzing systems in a graphic environment and has applications in control systems and digital signal processing. The VHDL code is generated from HDL Coder, another tool in MATLAB software, generating synthesizable Verilog and VHDL code, from the MATLAB functions and Simulink models. The results obtained of processed data from the system are analyzed and validated, comparing the reference data generated from Wireless Waveform Generator toolbox in MATLAB.