A boundary scan based one channel timing analyser

Detalhes bibliográficos
Autor(a) principal: Gustavo Costa Alves
Data de Publicação: 1999
Outros Autores: José Martins Ferreira
Tipo de documento: Livro
Idioma: eng
Título da fonte: Repositório Científico de Acesso Aberto de Portugal (Repositórios Cientìficos)
Texto Completo: https://hdl.handle.net/10216/85002
Resumo: The boundary scan test infrastructure is now widely implemented in the integrated circuit market, especially in the microprocessor and Application-Specific Integrated Circuit arena. While the structural test of printed circuit boards has been considered the driving force behind its broad acceptance, the test community has also addressed the issues of prototype debug and validation. However, the more demanding requirements associated with these issues are not sufficiently covered by the mandatory and optional operating modes described in the IEEE 1149.1 standard, especially for debugging problems associated with real-time operations. Previous work has focused on this problem, having resulted in a new set of user-defined optional instructions addressing the use of the BS register to store in real-time a sequence of contiguous vectors, captured at its parallel inputs without / until / after a certain condition is found. In this paper we describe the trade-off between input channels and storage capacity, by proposing a new operating mode where the BS register is used to capture / store an n-bit sequence captured at one single functional pin, thus acting similarly to a one-channel timing analyser. This non-intrusive operating mode may also be used for field diagnosis and other on-line operations.
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spelling A boundary scan based one channel timing analyserEngenharia electrotécnica, Engenharia electrotécnica, electrónica e informáticaElectrical engineering, Electrical engineering, Electronic engineering, Information engineeringThe boundary scan test infrastructure is now widely implemented in the integrated circuit market, especially in the microprocessor and Application-Specific Integrated Circuit arena. While the structural test of printed circuit boards has been considered the driving force behind its broad acceptance, the test community has also addressed the issues of prototype debug and validation. However, the more demanding requirements associated with these issues are not sufficiently covered by the mandatory and optional operating modes described in the IEEE 1149.1 standard, especially for debugging problems associated with real-time operations. Previous work has focused on this problem, having resulted in a new set of user-defined optional instructions addressing the use of the BS register to store in real-time a sequence of contiguous vectors, captured at its parallel inputs without / until / after a certain condition is found. In this paper we describe the trade-off between input channels and storage capacity, by proposing a new operating mode where the BS register is used to capture / store an n-bit sequence captured at one single functional pin, thus acting similarly to a one-channel timing analyser. This non-intrusive operating mode may also be used for field diagnosis and other on-line operations.19991999-01-01T00:00:00Zinfo:eu-repo/semantics/publishedVersioninfo:eu-repo/semantics/bookapplication/pdfhttps://hdl.handle.net/10216/85002engGustavo Costa AlvesJosé Martins Ferreirainfo:eu-repo/semantics/openAccessreponame:Repositório Científico de Acesso Aberto de Portugal (Repositórios Cientìficos)instname:Agência para a Sociedade do Conhecimento (UMIC) - FCT - Sociedade da Informaçãoinstacron:RCAAP2023-11-29T14:38:43Zoai:repositorio-aberto.up.pt:10216/85002Portal AgregadorONGhttps://www.rcaap.pt/oai/openaireopendoar:71602024-03-20T00:05:51.893693Repositório Científico de Acesso Aberto de Portugal (Repositórios Cientìficos) - Agência para a Sociedade do Conhecimento (UMIC) - FCT - Sociedade da Informaçãofalse
dc.title.none.fl_str_mv A boundary scan based one channel timing analyser
title A boundary scan based one channel timing analyser
spellingShingle A boundary scan based one channel timing analyser
Gustavo Costa Alves
Engenharia electrotécnica, Engenharia electrotécnica, electrónica e informática
Electrical engineering, Electrical engineering, Electronic engineering, Information engineering
title_short A boundary scan based one channel timing analyser
title_full A boundary scan based one channel timing analyser
title_fullStr A boundary scan based one channel timing analyser
title_full_unstemmed A boundary scan based one channel timing analyser
title_sort A boundary scan based one channel timing analyser
author Gustavo Costa Alves
author_facet Gustavo Costa Alves
José Martins Ferreira
author_role author
author2 José Martins Ferreira
author2_role author
dc.contributor.author.fl_str_mv Gustavo Costa Alves
José Martins Ferreira
dc.subject.por.fl_str_mv Engenharia electrotécnica, Engenharia electrotécnica, electrónica e informática
Electrical engineering, Electrical engineering, Electronic engineering, Information engineering
topic Engenharia electrotécnica, Engenharia electrotécnica, electrónica e informática
Electrical engineering, Electrical engineering, Electronic engineering, Information engineering
description The boundary scan test infrastructure is now widely implemented in the integrated circuit market, especially in the microprocessor and Application-Specific Integrated Circuit arena. While the structural test of printed circuit boards has been considered the driving force behind its broad acceptance, the test community has also addressed the issues of prototype debug and validation. However, the more demanding requirements associated with these issues are not sufficiently covered by the mandatory and optional operating modes described in the IEEE 1149.1 standard, especially for debugging problems associated with real-time operations. Previous work has focused on this problem, having resulted in a new set of user-defined optional instructions addressing the use of the BS register to store in real-time a sequence of contiguous vectors, captured at its parallel inputs without / until / after a certain condition is found. In this paper we describe the trade-off between input channels and storage capacity, by proposing a new operating mode where the BS register is used to capture / store an n-bit sequence captured at one single functional pin, thus acting similarly to a one-channel timing analyser. This non-intrusive operating mode may also be used for field diagnosis and other on-line operations.
publishDate 1999
dc.date.none.fl_str_mv 1999
1999-01-01T00:00:00Z
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dc.identifier.uri.fl_str_mv https://hdl.handle.net/10216/85002
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dc.language.iso.fl_str_mv eng
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collection Repositório Científico de Acesso Aberto de Portugal (Repositórios Cientìficos)
repository.name.fl_str_mv Repositório Científico de Acesso Aberto de Portugal (Repositórios Cientìficos) - Agência para a Sociedade do Conhecimento (UMIC) - FCT - Sociedade da Informação
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