Modeling and FPGA-based implementation of an efficient and simple envelope detector using a Hilbert Transform FIR filter for ultrasound imaging applications

Detalhes bibliográficos
Autor(a) principal: Assef,Amauri Amorin
Data de Publicação: 2018
Outros Autores: Ferreira,Breno Mendes, Maia,Joaquim Miguel, Costa,Eduardo Tavares
Tipo de documento: Relatório
Idioma: eng
Título da fonte: Research on Biomedical Engineering (Online)
Texto Completo: http://old.scielo.br/scielo.php?script=sci_arttext&pid=S2446-47402018000100087
Resumo: Abstract Introduction Although the envelope detection is a widely used method in medical ultrasound (US) imaging to demodulate the amplitude of the received echo signal before any back-end processing, novel hardware-based approaches have been proposed for reducing its computational cost and complexity. In this paper, we present the modeling and FPGA implementation of an efficient envelope detector based on a Hilbert Transform (HT) approximation for US imaging applications. Method The proposed model exploits both the symmetry and the alternating zero-valued coefficients of a HT finite impulse response (FIR) filter to generate the in-phase and quadrature components that are necessary for the envelope computation. The hardware design was synthesized for a Stratix IV FPGA, by using the Simulink and the integrated DSP Builder toolbox, and implemented on a Terasic DE4-230 board. The accuracy of our algorithm was evaluated by the normalized root mean square error (NRMSE) cost function in comparison with the conventional method based on the absolute value of the discrete-time analytic signal via FFT. Results An excellent agreement was achieved between the theoretical simulations with the experimental result. The NRMSE was 0.42% and the overall FPGA utilization was less than 1.5%. Additionally, the proposed envelope detector is capable of generating envelope data at every FPGA clock cycle after 19 (0.48 µs) cycles of latency. Conclusion The presented results corroborate the simplicity, flexibility and efficiency of our model for generating US envelope data in real-time, while reducing the hardware cost by up to 75%.
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spelling Modeling and FPGA-based implementation of an efficient and simple envelope detector using a Hilbert Transform FIR filter for ultrasound imaging applicationsUltrasoundEnvelope detectionHilbert transformFPGASimulinkAbstract Introduction Although the envelope detection is a widely used method in medical ultrasound (US) imaging to demodulate the amplitude of the received echo signal before any back-end processing, novel hardware-based approaches have been proposed for reducing its computational cost and complexity. In this paper, we present the modeling and FPGA implementation of an efficient envelope detector based on a Hilbert Transform (HT) approximation for US imaging applications. Method The proposed model exploits both the symmetry and the alternating zero-valued coefficients of a HT finite impulse response (FIR) filter to generate the in-phase and quadrature components that are necessary for the envelope computation. The hardware design was synthesized for a Stratix IV FPGA, by using the Simulink and the integrated DSP Builder toolbox, and implemented on a Terasic DE4-230 board. The accuracy of our algorithm was evaluated by the normalized root mean square error (NRMSE) cost function in comparison with the conventional method based on the absolute value of the discrete-time analytic signal via FFT. Results An excellent agreement was achieved between the theoretical simulations with the experimental result. The NRMSE was 0.42% and the overall FPGA utilization was less than 1.5%. Additionally, the proposed envelope detector is capable of generating envelope data at every FPGA clock cycle after 19 (0.48 µs) cycles of latency. Conclusion The presented results corroborate the simplicity, flexibility and efficiency of our model for generating US envelope data in real-time, while reducing the hardware cost by up to 75%.Sociedade Brasileira de Engenharia Biomédica2018-01-01info:eu-repo/semantics/reportinfo:eu-repo/semantics/publishedVersiontext/htmlhttp://old.scielo.br/scielo.php?script=sci_arttext&pid=S2446-47402018000100087Research on Biomedical Engineering v.34 n.1 2018reponame:Research on Biomedical Engineering (Online)instname:Sociedade Brasileira de Engenharia Biomédica (SBEB)instacron:SBEB10.1590/2446-4740.02417info:eu-repo/semantics/openAccessAssef,Amauri AmorinFerreira,Breno MendesMaia,Joaquim MiguelCosta,Eduardo Tavareseng2018-04-18T00:00:00Zoai:scielo:S2446-47402018000100087Revistahttp://www.rbejournal.org/https://old.scielo.br/oai/scielo-oai.php||rbe@rbejournal.org2446-47402446-4732opendoar:2018-04-18T00:00Research on Biomedical Engineering (Online) - Sociedade Brasileira de Engenharia Biomédica (SBEB)false
dc.title.none.fl_str_mv Modeling and FPGA-based implementation of an efficient and simple envelope detector using a Hilbert Transform FIR filter for ultrasound imaging applications
title Modeling and FPGA-based implementation of an efficient and simple envelope detector using a Hilbert Transform FIR filter for ultrasound imaging applications
spellingShingle Modeling and FPGA-based implementation of an efficient and simple envelope detector using a Hilbert Transform FIR filter for ultrasound imaging applications
Assef,Amauri Amorin
Ultrasound
Envelope detection
Hilbert transform
FPGA
Simulink
title_short Modeling and FPGA-based implementation of an efficient and simple envelope detector using a Hilbert Transform FIR filter for ultrasound imaging applications
title_full Modeling and FPGA-based implementation of an efficient and simple envelope detector using a Hilbert Transform FIR filter for ultrasound imaging applications
title_fullStr Modeling and FPGA-based implementation of an efficient and simple envelope detector using a Hilbert Transform FIR filter for ultrasound imaging applications
title_full_unstemmed Modeling and FPGA-based implementation of an efficient and simple envelope detector using a Hilbert Transform FIR filter for ultrasound imaging applications
title_sort Modeling and FPGA-based implementation of an efficient and simple envelope detector using a Hilbert Transform FIR filter for ultrasound imaging applications
author Assef,Amauri Amorin
author_facet Assef,Amauri Amorin
Ferreira,Breno Mendes
Maia,Joaquim Miguel
Costa,Eduardo Tavares
author_role author
author2 Ferreira,Breno Mendes
Maia,Joaquim Miguel
Costa,Eduardo Tavares
author2_role author
author
author
dc.contributor.author.fl_str_mv Assef,Amauri Amorin
Ferreira,Breno Mendes
Maia,Joaquim Miguel
Costa,Eduardo Tavares
dc.subject.por.fl_str_mv Ultrasound
Envelope detection
Hilbert transform
FPGA
Simulink
topic Ultrasound
Envelope detection
Hilbert transform
FPGA
Simulink
description Abstract Introduction Although the envelope detection is a widely used method in medical ultrasound (US) imaging to demodulate the amplitude of the received echo signal before any back-end processing, novel hardware-based approaches have been proposed for reducing its computational cost and complexity. In this paper, we present the modeling and FPGA implementation of an efficient envelope detector based on a Hilbert Transform (HT) approximation for US imaging applications. Method The proposed model exploits both the symmetry and the alternating zero-valued coefficients of a HT finite impulse response (FIR) filter to generate the in-phase and quadrature components that are necessary for the envelope computation. The hardware design was synthesized for a Stratix IV FPGA, by using the Simulink and the integrated DSP Builder toolbox, and implemented on a Terasic DE4-230 board. The accuracy of our algorithm was evaluated by the normalized root mean square error (NRMSE) cost function in comparison with the conventional method based on the absolute value of the discrete-time analytic signal via FFT. Results An excellent agreement was achieved between the theoretical simulations with the experimental result. The NRMSE was 0.42% and the overall FPGA utilization was less than 1.5%. Additionally, the proposed envelope detector is capable of generating envelope data at every FPGA clock cycle after 19 (0.48 µs) cycles of latency. Conclusion The presented results corroborate the simplicity, flexibility and efficiency of our model for generating US envelope data in real-time, while reducing the hardware cost by up to 75%.
publishDate 2018
dc.date.none.fl_str_mv 2018-01-01
dc.type.driver.fl_str_mv info:eu-repo/semantics/report
dc.type.status.fl_str_mv info:eu-repo/semantics/publishedVersion
format report
status_str publishedVersion
dc.identifier.uri.fl_str_mv http://old.scielo.br/scielo.php?script=sci_arttext&pid=S2446-47402018000100087
url http://old.scielo.br/scielo.php?script=sci_arttext&pid=S2446-47402018000100087
dc.language.iso.fl_str_mv eng
language eng
dc.relation.none.fl_str_mv 10.1590/2446-4740.02417
dc.rights.driver.fl_str_mv info:eu-repo/semantics/openAccess
eu_rights_str_mv openAccess
dc.format.none.fl_str_mv text/html
dc.publisher.none.fl_str_mv Sociedade Brasileira de Engenharia Biomédica
publisher.none.fl_str_mv Sociedade Brasileira de Engenharia Biomédica
dc.source.none.fl_str_mv Research on Biomedical Engineering v.34 n.1 2018
reponame:Research on Biomedical Engineering (Online)
instname:Sociedade Brasileira de Engenharia Biomédica (SBEB)
instacron:SBEB
instname_str Sociedade Brasileira de Engenharia Biomédica (SBEB)
instacron_str SBEB
institution SBEB
reponame_str Research on Biomedical Engineering (Online)
collection Research on Biomedical Engineering (Online)
repository.name.fl_str_mv Research on Biomedical Engineering (Online) - Sociedade Brasileira de Engenharia Biomédica (SBEB)
repository.mail.fl_str_mv ||rbe@rbejournal.org
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