Implementação de redes neurais convolucionais em plataforma de rede intra-chip

• Autor(a) principal: Cardoso, Alexandre Nietupski
• Data de Publicação: 2022
• Outros Autores: [e-mail]
• Tipo de documento: Dissertação
• Idioma: por
• Título da fonte: Biblioteca Digital de Teses e Dissertações da UERJ
• Texto Completo: http://www.bdtd.uerj.br/handle/1/19334
• topic: Computer learning; Neural networks (Computing); On-chip programmable systems; Electronic engineering; Engenharia eletrônica; Aprendizado do computador; Redes neurais (Computação); Sistemas programáveis em chip; ENGENHARIAS::ENGENHARIA ELETRICA::ELETRONICA INDUSTRIAL, SISTEMAS E CONTROLES ELETRONICOS

The interest in accelerative approaches for executing Machine Learning models is intense, since applying methods from this field to a growing set of situations is a market demand and an industry tendency. On the other hand, the advance of integration technologies allows aggregating to multiprocessor embedded systems a growing number of modules and that gives to these systems enormous computational capacity, making it attractive for Artificial Intelligence solutions. However, these modules shall be connected efficiently and this is where Networks on Chip come to help, enabling the design of extremely capable and versatile embedded systems. In this work, we discuss the implementation of a convolutional neural network in a multiprocessor embedded system.Our emphasis was on organizing the implementation considering the application’s dataflow, pursuing the best possible use of parallel computing. Limitations related to the support for floating-point arithmetic in the chosen simulation environment restricted the performance of our implementation as a predictive model, but it did not prevent us from achieving our goal: to accelerate the execution of a convolutional neural network.