Mechanised local deadlock analysis based on timed behavioural patterns and responsiveness

Detalhes bibliográficos
Autor(a) principal: JESUS JÚNIOR, Joabe Bezerra de
Data de Publicação: 2023
Tipo de documento: Tese
Idioma: eng
Título da fonte: Repositório Institucional da UFPE
Texto Completo: https://repositorio.ufpe.br/handle/123456789/54314
Resumo: SAMPAIO, Augusto C. A., também é conhecido em citações bibliográficas por: SAMPAIO, Augusto Cezar Alves.
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spelling JESUS JÚNIOR, Joabe Bezerra dehttp://lattes.cnpq.br/5758754427967778http://lattes.cnpq.br/3977760354511853SAMPAIO, Augusto C. A.2023-12-21T17:36:27Z2023-12-21T17:36:27Z2023-08-28JESUS JÚNIOR, Joabe Bezerra de. Mechanised local deadlock analysis based on timed behavioural patterns and responsiveness. 2023. Tese (Doutorado em Ciência da Computação) – Universidade Federal de Pernambuco, Recife, 2023.https://repositorio.ufpe.br/handle/123456789/54314SAMPAIO, Augusto C. A., também é conhecido em citações bibliográficas por: SAMPAIO, Augusto Cezar Alves.Although semi-formal model driven development (MDD) helps the identification of design problems in the early stages of the development using simulation environments such as Matlab/SIMULINK, the most recent guidelines for verification in this context (such as DO178C) suggest the use of formal verification for such systems. In this context, many approaches have been proposed to perform translations from SIMULINK to a target formal notation. However, most of these approaches are not focused on compositional verification to allow scalability; or do not provide traceability of the formal verification results. To provide a compositional deadlock analysis for timed process networks, more specifically, those obtained from SIMULINK discrete multi-rate block diagrams, we present a strategy that uses Communicating Sequential Processes (CSP) to verify these models. The strategy extends the Roscoe and Dathi’s compositional deadlock analysis theory by adding time. Moreover, the approach handles both: models with an acyclic communication graph; and cyclic models, which naturally happens in SIMULINK models with feedback, among other kinds of cycles. Since there is no general solution to analyse cyclic models in a compositional way, we explore the use of behavioural patterns that allow the verification to be carried out in a compositional fashion. Besides, we devise a verification approach for the integration of systems by extending the notion of responsive plug-ins from Roscoe, Reed and Sinclair. We represent process networks in tock-CSP, a dialect of CSP that allows modelling time aspects using a special tock event. The verification approach is encoded in CSP-Prover, a theorem prover for CSP which is itself implemented in Isabelle/HOL. To illustrate the overall approach and, particularly, how it can scale, we consider an example of an actuation system with increasing complexity for the longitudinal control of an aircraft, including an Elevator Control System and an example of an active Stall Control System. We show that the examples are instances of the considered timed behaviour patterns. These patterns and all verification steps are formalised using CSP-Prover. Soundness is based on a Galois connection linking the traces semantics of the generated tock-CSP specification and simulation trajectories resulting from an encoding in Isabelle/HOL of the Bouissou and Chapoutot’s operational semantics theory for SIMULINK.Embora o Desenvolvimento Dirigido por Modelos (MDD do inglês model driven de- velopment) semi-formal auxilie a identificação de problemas no design nas fases iniciais do desenvolvimento com o uso de ambientes de simulação como o Matlab/SIMULINK, os guias mais recentes para a verificação neste contexto (como a DO178C) sugerem o uso de verificação formal para estes sistemas. Neste contexto, várias abordagens vêm sendo propostas para realizar a tradução de SIMULINK para uma notação formal. Entretanto, a maioria dessas abordagens não é focada na verificação composicional para permitir escalabilidade; ou não provê a ras- treabilidade dos resultados da verificação formal. Para prover uma análise composicional de deadlock para redes de process temporizadas, mais especificamente, aquelas obtidas a partir de diagramas de bloco multi-taxa discretos do SIMULINK, apresentamos uma estratégia que usa a notação Communicating Sequential Processes (CSP) para verificar estes modelos. A estratégia estende a teoria de análise composicional de deadlock de Roscoe e Dathi adicionando tempo. Ademais, a abordagem trata tanto modelos com um grafo de comunicação acíclico quanto mod- elos cíclicos, que ocorrem naturalmente em modelos SIMULINK com realimentação (feedback), entre outros tipos de ciclos. Uma vez que não existe uma solução geral para analisar modelos cíclicos de forma composicional, exploramos o uso de padrões comportamentais que permitem que a verificação seja realizada de forma composicional. Além disso, concebemos uma abor- dagem de verificação para a integração de sistemas, estendendo a noção de plug-ins responsivos de Roscoe, Reed e Sinclair. Representamos redes de processo em tock-CSP, um dialeto de CSP que permite modelar aspectos de tempo usando o evento especial tock. A abordagem de verificação é codificada em CSP-Prover, um provador de teoremas para CSP que é codificado em Isabelle/HOL. Para ilustrar a abordagem geral e, particularmente, como ela pode escalar, consideramos, de forma crescente, diferentes níveis de complexidade de um sistema de atuação para o controle longitudinal de uma aeronave, incluindo um Sistema de Controle de Arfagem e um Sistema de Controle de Estol. Mostramos que os exemplos são instâncias dos padrões de comportamento temporizado considerados. Os padrões e todas as etapas de verificação são formalizadas usando CSP-Prover. A corretude é baseada em uma conexão de Galois ligando a semântica de traces da especificação tock-CSP gerada e as trajetórias de simulação resultantes de uma codificação em Isabelle/HOL da teoria de semântica operacional para SIMULINK de Bouissou e Chapoutot.engUniversidade Federal de PernambucoPrograma de Pos Graduacao em Ciencia da ComputacaoUFPEBrasilhttp://creativecommons.org/licenses/by-nc-nd/3.0/br/info:eu-repo/semantics/embargoedAccessControl systemsSimulinkTock-CSPDeadlockPatternsResponsivenessMechanised local deadlock analysis based on timed behavioural patterns and responsivenessinfo:eu-repo/semantics/publishedVersioninfo:eu-repo/semantics/doctoralThesisdoutoradoreponame:Repositório Institucional da UFPEinstname:Universidade Federal de Pernambuco (UFPE)instacron:UFPECC-LICENSElicense_rdflicense_rdfapplication/rdf+xml; charset=utf-8811https://repositorio.ufpe.br/bitstream/123456789/54314/2/license_rdfe39d27027a6cc9cb039ad269a5db8e34MD52LICENSElicense.txtlicense.txttext/plain; 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dc.title.pt_BR.fl_str_mv Mechanised local deadlock analysis based on timed behavioural patterns and responsiveness
title Mechanised local deadlock analysis based on timed behavioural patterns and responsiveness
spellingShingle Mechanised local deadlock analysis based on timed behavioural patterns and responsiveness
JESUS JÚNIOR, Joabe Bezerra de
Control systems
Simulink
Tock-CSP
Deadlock
Patterns
Responsiveness
title_short Mechanised local deadlock analysis based on timed behavioural patterns and responsiveness
title_full Mechanised local deadlock analysis based on timed behavioural patterns and responsiveness
title_fullStr Mechanised local deadlock analysis based on timed behavioural patterns and responsiveness
title_full_unstemmed Mechanised local deadlock analysis based on timed behavioural patterns and responsiveness
title_sort Mechanised local deadlock analysis based on timed behavioural patterns and responsiveness
author JESUS JÚNIOR, Joabe Bezerra de
author_facet JESUS JÚNIOR, Joabe Bezerra de
author_role author
dc.contributor.authorLattes.pt_BR.fl_str_mv http://lattes.cnpq.br/5758754427967778
dc.contributor.advisorLattes.pt_BR.fl_str_mv http://lattes.cnpq.br/3977760354511853
dc.contributor.author.fl_str_mv JESUS JÚNIOR, Joabe Bezerra de
dc.contributor.advisor1.fl_str_mv SAMPAIO, Augusto C. A.
contributor_str_mv SAMPAIO, Augusto C. A.
dc.subject.por.fl_str_mv Control systems
Simulink
Tock-CSP
Deadlock
Patterns
Responsiveness
topic Control systems
Simulink
Tock-CSP
Deadlock
Patterns
Responsiveness
description SAMPAIO, Augusto C. A., também é conhecido em citações bibliográficas por: SAMPAIO, Augusto Cezar Alves.
publishDate 2023
dc.date.accessioned.fl_str_mv 2023-12-21T17:36:27Z
dc.date.available.fl_str_mv 2023-12-21T17:36:27Z
dc.date.issued.fl_str_mv 2023-08-28
dc.type.status.fl_str_mv info:eu-repo/semantics/publishedVersion
dc.type.driver.fl_str_mv info:eu-repo/semantics/doctoralThesis
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status_str publishedVersion
dc.identifier.citation.fl_str_mv JESUS JÚNIOR, Joabe Bezerra de. Mechanised local deadlock analysis based on timed behavioural patterns and responsiveness. 2023. Tese (Doutorado em Ciência da Computação) – Universidade Federal de Pernambuco, Recife, 2023.
dc.identifier.uri.fl_str_mv https://repositorio.ufpe.br/handle/123456789/54314
identifier_str_mv JESUS JÚNIOR, Joabe Bezerra de. Mechanised local deadlock analysis based on timed behavioural patterns and responsiveness. 2023. Tese (Doutorado em Ciência da Computação) – Universidade Federal de Pernambuco, Recife, 2023.
url https://repositorio.ufpe.br/handle/123456789/54314
dc.language.iso.fl_str_mv eng
language eng
dc.rights.driver.fl_str_mv http://creativecommons.org/licenses/by-nc-nd/3.0/br/
info:eu-repo/semantics/embargoedAccess
rights_invalid_str_mv http://creativecommons.org/licenses/by-nc-nd/3.0/br/
eu_rights_str_mv embargoedAccess
dc.publisher.none.fl_str_mv Universidade Federal de Pernambuco
dc.publisher.program.fl_str_mv Programa de Pos Graduacao em Ciencia da Computacao
dc.publisher.initials.fl_str_mv UFPE
dc.publisher.country.fl_str_mv Brasil
publisher.none.fl_str_mv Universidade Federal de Pernambuco
dc.source.none.fl_str_mv reponame:Repositório Institucional da UFPE
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