Energy/quality-aware hardware solutions for the residual coding loop components of the high efficiency video coding standard
Autor(a) principal: | |
---|---|
Data de Publicação: | 2018 |
Tipo de documento: | Dissertação |
Idioma: | por |
Título da fonte: | Repositório Institucional da UFPel - Guaiaca |
Texto Completo: | http://guaiaca.ufpel.edu.br/handle/prefix/8523 |
Resumo: | Multimedia applications, such as digital videos, are very popular nowadays, especially on mobile devices. Moreover, there is an expectation of continuous growth of the Internet-based digital videos traffic throughout the next years. Video coders, e.g. the High Efficiency Video Coding (HEVC), are very important in this context as the video coders can rationalize Internet resources by reducing the amount of video-related data flowing through the network. Unfortunately, this data reduction requires a huge computational effort. Thus, hardware accelerators can be used as a feasible solution, providing high-throughput on low-power. The HEVC residual coding loop (RCL), composed of direct transform, direct quantization, inverse quantization, and inverse transform, is a highly-requested stage of video coding standards since it is used multiple times to test several coding modes (CMs). Therefore, the objective of this work is to provide multiple energy/quality-aware dedicated hardware solutions to increase throughput for the components of RCL in HEVC, allowing real time processing of many CM by the RCL. Thus, the HEVC encoder using the presented solutions is expected to be more coding efficient than the ones using the solution proposed by the existing related works. Innovative solutions are proposed in this work to increase throughput, which has direct impact on the coding efficiency in the RCL components, with low power dissipation. A direct DCT was proposed based on the Fast Fourier Transform (FFT), which allows an intensive hardware reuse, and energy-consumption reduction, able to operate up to 2.54 GHz while dissipating 12.33 mW of power; an energy/quality scalable inverse DCT is presented using a bypass engine based on statistical analysis, setting a trade-off between coding-efficiency and energy-efficiency, which operates up to 737.46 MHz and dissipates between 13.87 mW and 16.84 mW; and a project space exploration of quantization architectures is also presented, with power dissipation of 152.13 mW and 31.15 mW at 888.10 Mhz and 1.36 GHz, respectively, including an integrated direct/inverse quantization, which reduces the number of arithmetical operations by integrating direct quantization and inverse quantization, dissipating 369.37 mW at 1.68 GHz. The developed hardware architectures are able to process up to 108, 32, 38, 58, and 72 CM of UHD 4K videos at 60fps for the DCT, IDCT, direct quantization, inverse quantization, and integrated direct/inverse quantization hardware architectures, respectively. When compared with related works, the developed RCL components hardware architectures can operate on higher frequencies, present higher throughputs, and are more energy efficient. |
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2022-07-15T16:59:13Z2022-07-15T16:59:13Z2018BRAATZ, Luciano Almeida. Energy/Quality-Aware Hardware Solutions for the Residual Coding Loop Components of the High Efficiency Video Coding Standard. 2018. 111 f. Dissertação (Mestrado em Ciência da Computação) – Programa de Pós-Graduação em Computação, Centro de Desenvolvimento Tecnológico, Universidade Federal de Pelotas, Pelotas, 2018.http://guaiaca.ufpel.edu.br/handle/prefix/8523Multimedia applications, such as digital videos, are very popular nowadays, especially on mobile devices. Moreover, there is an expectation of continuous growth of the Internet-based digital videos traffic throughout the next years. Video coders, e.g. the High Efficiency Video Coding (HEVC), are very important in this context as the video coders can rationalize Internet resources by reducing the amount of video-related data flowing through the network. Unfortunately, this data reduction requires a huge computational effort. Thus, hardware accelerators can be used as a feasible solution, providing high-throughput on low-power. The HEVC residual coding loop (RCL), composed of direct transform, direct quantization, inverse quantization, and inverse transform, is a highly-requested stage of video coding standards since it is used multiple times to test several coding modes (CMs). Therefore, the objective of this work is to provide multiple energy/quality-aware dedicated hardware solutions to increase throughput for the components of RCL in HEVC, allowing real time processing of many CM by the RCL. Thus, the HEVC encoder using the presented solutions is expected to be more coding efficient than the ones using the solution proposed by the existing related works. Innovative solutions are proposed in this work to increase throughput, which has direct impact on the coding efficiency in the RCL components, with low power dissipation. A direct DCT was proposed based on the Fast Fourier Transform (FFT), which allows an intensive hardware reuse, and energy-consumption reduction, able to operate up to 2.54 GHz while dissipating 12.33 mW of power; an energy/quality scalable inverse DCT is presented using a bypass engine based on statistical analysis, setting a trade-off between coding-efficiency and energy-efficiency, which operates up to 737.46 MHz and dissipates between 13.87 mW and 16.84 mW; and a project space exploration of quantization architectures is also presented, with power dissipation of 152.13 mW and 31.15 mW at 888.10 Mhz and 1.36 GHz, respectively, including an integrated direct/inverse quantization, which reduces the number of arithmetical operations by integrating direct quantization and inverse quantization, dissipating 369.37 mW at 1.68 GHz. The developed hardware architectures are able to process up to 108, 32, 38, 58, and 72 CM of UHD 4K videos at 60fps for the DCT, IDCT, direct quantization, inverse quantization, and integrated direct/inverse quantization hardware architectures, respectively. When compared with related works, the developed RCL components hardware architectures can operate on higher frequencies, present higher throughputs, and are more energy efficient.Aplicações multimídia, como vídeos digitais, são muito populares hoje em dia, especialmente em dispositivos móveis. Além disso, há uma expectativa de crescimento contínuo do tráfego de vídeos digitais baseados na Internet nos próximos anos. Codificadores de vídeo, como o HEVC (do inglês High-Efficiency Video Coding), são muito importantes neste contexto, pois os codificadores de vídeo podem racionalizar os recursos da Internet reduzindo o tráfego de dados relacionados a vídeos na rede. Infelizmente, essa redução no volume de dados requer um enorme esforço computacional. Assim, o uso de aceleradores de hardware se apresenta como uma solução viável, pela sua capacidade de apresentar alto throughput e baixo consumo energético. O laço de codificação residual do HEVC (RCL, do inglês Residual Coding Loop), composto por transformada direta, quantificação direta, quantização inversa e transformada inversa, é um estágio altamente solicitado de padrões de codificação de vídeo, pois é usado para testar vários modos de codificação. Portanto, o objetivo deste trabalho é fornecer soluções de hardware dedicadas com foco em eficiência energética e no aumento do throughput dos componentes do RCL no HEVC, permitindo que os componentes do RCL possam processar diversos modos de codificação em tempo real. Assim, o codificador HEVC que usa as soluções apresentadas deverá ser mais eficiente em termos de codificação do que os que usam as soluções propostas pelos trabalhos relacionados existentes. Este trabalho propõe soluções inovadoras para aumentar o throughput dos componentes do RCL, com impacto direto na eficiência de codificação e baixa dissipação de energia. A DCT, proposta com base na Transformada Rápida de Fourier (FFT, do inglês Fast Fourier Transform), permite a reutilização intensiva de hardware e redução de consumo de energia, sendo capaz de operar a até 2,54 GHz enquanto dissipa 12,33 mW de potência; uma IDCT com compromisso entre energia e qualidade é apresentada usando um mecanismo de bypass com base em análise estatística, estabelecendo um compromisso entre eficiência de codificação e eficiência energética, opera até 737,46 MHz e dissipa entre 13,87 mW e 16,84 mW; uma exploração do espaço de projeto de arquiteturas de quantização também é apresentada, com uma dissipação de potência entre 152,13 mW e 31,15 mW a 888,10 Mhz e 1,36 GHz, respectivamente; um módulo integrado de quantização direta e inversa que reduz o número de operações aritméticas integrando quantização direta e quantificação inversa, dissipando 369,37 mW a 1,68 GHz. As arquiteturas de hardware desenvolvidas são capazes de processar até 108, 32, 38, 58 e 72 modos de codificação de vídeos UHD 4K a 60fps para DCT, IDCT, quantização direta, quantização inversa e a arquitetura integrada de quantização direta e inversa, respectivamente. Comparado aos trabalhos relacionados, as arquiteturas de hardware dedicadas para os componentes da RCL operam com frequências mais altas, apresentam throughputs maiores e são mais eficientes energeticamente.Sem bolsaporUniversidade Federal de PelotasPrograma de Pós-Graduação em ComputaçãoUFPelBrasilCentro de Desenvolvimento TecnológicoCNPQ::CIENCIAS EXATAS E DA TERRA::CIENCIA DA COMPUTACAOComputaçãoVideo codingHEVCResidual coding loopHardware designEnergy/quality awarenessCodificação de vídeoLaço de codificação residualProjeto de hardwareFoco em qualidade e energiaEnergy/quality-aware hardware solutions for the residual coding loop components of the high efficiency video coding standardSoluções em Hardware com Foco em Aumento da Qualidade e Economia de Energia para os Componentes do Laço de Codificação Residual do Padrão HEVCinfo:eu-repo/semantics/publishedVersioninfo:eu-repo/semantics/masterThesisPalomino, Daniel MunariAgostini, Luciano VolcanPorto, Marcelo SchiavonBraatz, Luciano Almeidainfo:eu-repo/semantics/openAccessreponame:Repositório Institucional da UFPel - Guaiacainstname:Universidade Federal de Pelotas (UFPEL)instacron:UFPELTEXTDissertacao_Luciano_Almeida.pdf.txtDissertacao_Luciano_Almeida.pdf.txtExtracted texttext/plain209731http://guaiaca.ufpel.edu.br/xmlui/bitstream/prefix/8523/6/Dissertacao_Luciano_Almeida.pdf.txt80c2fbcb67c6d9237dfaa4bfe339dd90MD56open accessTHUMBNAILDissertacao_Luciano_Almeida.pdf.jpgDissertacao_Luciano_Almeida.pdf.jpgGenerated Thumbnailimage/jpeg1246http://guaiaca.ufpel.edu.br/xmlui/bitstream/prefix/8523/7/Dissertacao_Luciano_Almeida.pdf.jpg2fd6368dcb50cb81491de986b8dd93fdMD57open accessORIGINALDissertacao_Luciano_Almeida.pdfDissertacao_Luciano_Almeida.pdfapplication/pdf4704166http://guaiaca.ufpel.edu.br/xmlui/bitstream/prefix/8523/1/Dissertacao_Luciano_Almeida.pdf07034f6a1143ea756df75a74d71ba50fMD51open accessCC-LICENSElicense_urllicense_urltext/plain; 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dc.title.pt_BR.fl_str_mv |
Energy/quality-aware hardware solutions for the residual coding loop components of the high efficiency video coding standard |
dc.title.alternative.pt_BR.fl_str_mv |
Soluções em Hardware com Foco em Aumento da Qualidade e Economia de Energia para os Componentes do Laço de Codificação Residual do Padrão HEVC |
title |
Energy/quality-aware hardware solutions for the residual coding loop components of the high efficiency video coding standard |
spellingShingle |
Energy/quality-aware hardware solutions for the residual coding loop components of the high efficiency video coding standard Braatz, Luciano Almeida CNPQ::CIENCIAS EXATAS E DA TERRA::CIENCIA DA COMPUTACAO Computação Video coding HEVC Residual coding loop Hardware design Energy/quality awareness Codificação de vídeo Laço de codificação residual Projeto de hardware Foco em qualidade e energia |
title_short |
Energy/quality-aware hardware solutions for the residual coding loop components of the high efficiency video coding standard |
title_full |
Energy/quality-aware hardware solutions for the residual coding loop components of the high efficiency video coding standard |
title_fullStr |
Energy/quality-aware hardware solutions for the residual coding loop components of the high efficiency video coding standard |
title_full_unstemmed |
Energy/quality-aware hardware solutions for the residual coding loop components of the high efficiency video coding standard |
title_sort |
Energy/quality-aware hardware solutions for the residual coding loop components of the high efficiency video coding standard |
author |
Braatz, Luciano Almeida |
author_facet |
Braatz, Luciano Almeida |
author_role |
author |
dc.contributor.advisor-co1.fl_str_mv |
Palomino, Daniel Munari |
dc.contributor.advisor-co2.fl_str_mv |
Agostini, Luciano Volcan |
dc.contributor.advisor1.fl_str_mv |
Porto, Marcelo Schiavon |
dc.contributor.author.fl_str_mv |
Braatz, Luciano Almeida |
contributor_str_mv |
Palomino, Daniel Munari Agostini, Luciano Volcan Porto, Marcelo Schiavon |
dc.subject.cnpq.fl_str_mv |
CNPQ::CIENCIAS EXATAS E DA TERRA::CIENCIA DA COMPUTACAO |
topic |
CNPQ::CIENCIAS EXATAS E DA TERRA::CIENCIA DA COMPUTACAO Computação Video coding HEVC Residual coding loop Hardware design Energy/quality awareness Codificação de vídeo Laço de codificação residual Projeto de hardware Foco em qualidade e energia |
dc.subject.por.fl_str_mv |
Computação Video coding HEVC Residual coding loop Hardware design Energy/quality awareness Codificação de vídeo Laço de codificação residual Projeto de hardware Foco em qualidade e energia |
description |
Multimedia applications, such as digital videos, are very popular nowadays, especially on mobile devices. Moreover, there is an expectation of continuous growth of the Internet-based digital videos traffic throughout the next years. Video coders, e.g. the High Efficiency Video Coding (HEVC), are very important in this context as the video coders can rationalize Internet resources by reducing the amount of video-related data flowing through the network. Unfortunately, this data reduction requires a huge computational effort. Thus, hardware accelerators can be used as a feasible solution, providing high-throughput on low-power. The HEVC residual coding loop (RCL), composed of direct transform, direct quantization, inverse quantization, and inverse transform, is a highly-requested stage of video coding standards since it is used multiple times to test several coding modes (CMs). Therefore, the objective of this work is to provide multiple energy/quality-aware dedicated hardware solutions to increase throughput for the components of RCL in HEVC, allowing real time processing of many CM by the RCL. Thus, the HEVC encoder using the presented solutions is expected to be more coding efficient than the ones using the solution proposed by the existing related works. Innovative solutions are proposed in this work to increase throughput, which has direct impact on the coding efficiency in the RCL components, with low power dissipation. A direct DCT was proposed based on the Fast Fourier Transform (FFT), which allows an intensive hardware reuse, and energy-consumption reduction, able to operate up to 2.54 GHz while dissipating 12.33 mW of power; an energy/quality scalable inverse DCT is presented using a bypass engine based on statistical analysis, setting a trade-off between coding-efficiency and energy-efficiency, which operates up to 737.46 MHz and dissipates between 13.87 mW and 16.84 mW; and a project space exploration of quantization architectures is also presented, with power dissipation of 152.13 mW and 31.15 mW at 888.10 Mhz and 1.36 GHz, respectively, including an integrated direct/inverse quantization, which reduces the number of arithmetical operations by integrating direct quantization and inverse quantization, dissipating 369.37 mW at 1.68 GHz. The developed hardware architectures are able to process up to 108, 32, 38, 58, and 72 CM of UHD 4K videos at 60fps for the DCT, IDCT, direct quantization, inverse quantization, and integrated direct/inverse quantization hardware architectures, respectively. When compared with related works, the developed RCL components hardware architectures can operate on higher frequencies, present higher throughputs, and are more energy efficient. |
publishDate |
2018 |
dc.date.issued.fl_str_mv |
2018 |
dc.date.accessioned.fl_str_mv |
2022-07-15T16:59:13Z |
dc.date.available.fl_str_mv |
2022-07-15T16:59:13Z |
dc.type.status.fl_str_mv |
info:eu-repo/semantics/publishedVersion |
dc.type.driver.fl_str_mv |
info:eu-repo/semantics/masterThesis |
format |
masterThesis |
status_str |
publishedVersion |
dc.identifier.citation.fl_str_mv |
BRAATZ, Luciano Almeida. Energy/Quality-Aware Hardware Solutions for the Residual Coding Loop Components of the High Efficiency Video Coding Standard. 2018. 111 f. Dissertação (Mestrado em Ciência da Computação) – Programa de Pós-Graduação em Computação, Centro de Desenvolvimento Tecnológico, Universidade Federal de Pelotas, Pelotas, 2018. |
dc.identifier.uri.fl_str_mv |
http://guaiaca.ufpel.edu.br/handle/prefix/8523 |
identifier_str_mv |
BRAATZ, Luciano Almeida. Energy/Quality-Aware Hardware Solutions for the Residual Coding Loop Components of the High Efficiency Video Coding Standard. 2018. 111 f. Dissertação (Mestrado em Ciência da Computação) – Programa de Pós-Graduação em Computação, Centro de Desenvolvimento Tecnológico, Universidade Federal de Pelotas, Pelotas, 2018. |
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http://guaiaca.ufpel.edu.br/handle/prefix/8523 |
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por |
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info:eu-repo/semantics/openAccess |
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openAccess |
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Universidade Federal de Pelotas |
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Programa de Pós-Graduação em Computação |
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UFPel |
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Brasil |
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Centro de Desenvolvimento Tecnológico |
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Universidade Federal de Pelotas |
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