Motion estimation architecture using efficient adder-compressors for HDTV video coding
Autor(a) principal: | |
---|---|
Data de Publicação: | 2010 |
Outros Autores: | , , , |
Tipo de documento: | Artigo |
Idioma: | eng |
Título da fonte: | Repositório Institucional da UFRGS |
Texto Completo: | http://hdl.handle.net/10183/271367 |
Resumo: | This paper presents real time HDTV (High Definition Television) architecture for Motion Estimation(ME) using efficient adder compressors. The architecture is based on the Quarter Sub-sampledDiamond Search algorithm (QSDS) with Dynamic Iteration Control (DIC) algorithm. The main char-acteristic of the proposed architecture is the large amount of Processing Units (PUs) that are usedto calculate the SAD (Sum of Absolute Difference) metric. The internal structures of the PUs arecomposed by a large number of addition operations to calculate the SADs. In this paper, efficient 4-2 and 8-2 adder compressors are used in the PUs architecture to achieve the performance to workwith HDTV (High Definition Television) videos in real time at 30 frames per second. These addercompressors enable the simultaneous addition of 4 and 8 operands respectively. The PUs, usingadder compressors, were applied to the ME architecture. The implemented architecture wasdescribed in VHDL and synthesized to FPGA and, with Leonardo Spectrum tool, to the TSMC0.18μm CMOS standard cell technology. Synthesis results indicate that the new QSDS-DIC archi-tecture reach the best performance result and enable gains of 12% in terms of processing rate. Thearchitecture can reach real time for full HDTV (1920x1080 pixels) in the worst case processing 65frames per second, and it can process 269 HDTV frames per second in the average case. |
id |
UFRGS-2_13ca75f8ccd01d1c18cea9829fe6edd3 |
---|---|
oai_identifier_str |
oai:www.lume.ufrgs.br:10183/271367 |
network_acronym_str |
UFRGS-2 |
network_name_str |
Repositório Institucional da UFRGS |
repository_id_str |
|
spelling |
Porto, Marcelo SchiavonSilva, Andre Marcelo Coelho daAlmeida, SérgioCosta, Eduardo Antonio Cesar daBampi, Sergio2024-02-02T05:05:47Z20101807-1953http://hdl.handle.net/10183/271367000784517This paper presents real time HDTV (High Definition Television) architecture for Motion Estimation(ME) using efficient adder compressors. The architecture is based on the Quarter Sub-sampledDiamond Search algorithm (QSDS) with Dynamic Iteration Control (DIC) algorithm. The main char-acteristic of the proposed architecture is the large amount of Processing Units (PUs) that are usedto calculate the SAD (Sum of Absolute Difference) metric. The internal structures of the PUs arecomposed by a large number of addition operations to calculate the SADs. In this paper, efficient 4-2 and 8-2 adder compressors are used in the PUs architecture to achieve the performance to workwith HDTV (High Definition Television) videos in real time at 30 frames per second. These addercompressors enable the simultaneous addition of 4 and 8 operands respectively. The PUs, usingadder compressors, were applied to the ME architecture. The implemented architecture wasdescribed in VHDL and synthesized to FPGA and, with Leonardo Spectrum tool, to the TSMC0.18μm CMOS standard cell technology. Synthesis results indicate that the new QSDS-DIC archi-tecture reach the best performance result and enable gains of 12% in terms of processing rate. Thearchitecture can reach real time for full HDTV (1920x1080 pixels) in the worst case processing 65frames per second, and it can process 269 HDTV frames per second in the average case.application/pdfengJournal of integrated circuits and systems. Vol. 5, n. 1 (Mar. 2010), p. 78-88MicroeletrônicaCompressao : VideoMotion estimationFast algorithmHDTV video codingAdder compressorsMotion estimation architecture using efficient adder-compressors for HDTV video codinginfo:eu-repo/semantics/articleinfo:eu-repo/semantics/otherinfo:eu-repo/semantics/publishedVersioninfo:eu-repo/semantics/openAccessreponame:Repositório Institucional da UFRGSinstname:Universidade Federal do Rio Grande do Sul (UFRGS)instacron:UFRGSTEXT000784517.pdf.txt000784517.pdf.txtExtracted Texttext/plain49195http://www.lume.ufrgs.br/bitstream/10183/271367/2/000784517.pdf.txt035dfe53ebfa99ad12ae26935a420227MD52ORIGINAL000784517.pdfTexto completo (inglês)application/pdf905618http://www.lume.ufrgs.br/bitstream/10183/271367/1/000784517.pdf96e24a8eee183a9b91d89a1afc9d1baaMD5110183/2713672024-02-03 06:07:10.659849oai:www.lume.ufrgs.br:10183/271367Repositório de PublicaçõesPUBhttps://lume.ufrgs.br/oai/requestopendoar:2024-02-03T08:07:10Repositório Institucional da UFRGS - Universidade Federal do Rio Grande do Sul (UFRGS)false |
dc.title.pt_BR.fl_str_mv |
Motion estimation architecture using efficient adder-compressors for HDTV video coding |
title |
Motion estimation architecture using efficient adder-compressors for HDTV video coding |
spellingShingle |
Motion estimation architecture using efficient adder-compressors for HDTV video coding Porto, Marcelo Schiavon Microeletrônica Compressao : Video Motion estimation Fast algorithm HDTV video coding Adder compressors |
title_short |
Motion estimation architecture using efficient adder-compressors for HDTV video coding |
title_full |
Motion estimation architecture using efficient adder-compressors for HDTV video coding |
title_fullStr |
Motion estimation architecture using efficient adder-compressors for HDTV video coding |
title_full_unstemmed |
Motion estimation architecture using efficient adder-compressors for HDTV video coding |
title_sort |
Motion estimation architecture using efficient adder-compressors for HDTV video coding |
author |
Porto, Marcelo Schiavon |
author_facet |
Porto, Marcelo Schiavon Silva, Andre Marcelo Coelho da Almeida, Sérgio Costa, Eduardo Antonio Cesar da Bampi, Sergio |
author_role |
author |
author2 |
Silva, Andre Marcelo Coelho da Almeida, Sérgio Costa, Eduardo Antonio Cesar da Bampi, Sergio |
author2_role |
author author author author |
dc.contributor.author.fl_str_mv |
Porto, Marcelo Schiavon Silva, Andre Marcelo Coelho da Almeida, Sérgio Costa, Eduardo Antonio Cesar da Bampi, Sergio |
dc.subject.por.fl_str_mv |
Microeletrônica Compressao : Video |
topic |
Microeletrônica Compressao : Video Motion estimation Fast algorithm HDTV video coding Adder compressors |
dc.subject.eng.fl_str_mv |
Motion estimation Fast algorithm HDTV video coding Adder compressors |
description |
This paper presents real time HDTV (High Definition Television) architecture for Motion Estimation(ME) using efficient adder compressors. The architecture is based on the Quarter Sub-sampledDiamond Search algorithm (QSDS) with Dynamic Iteration Control (DIC) algorithm. The main char-acteristic of the proposed architecture is the large amount of Processing Units (PUs) that are usedto calculate the SAD (Sum of Absolute Difference) metric. The internal structures of the PUs arecomposed by a large number of addition operations to calculate the SADs. In this paper, efficient 4-2 and 8-2 adder compressors are used in the PUs architecture to achieve the performance to workwith HDTV (High Definition Television) videos in real time at 30 frames per second. These addercompressors enable the simultaneous addition of 4 and 8 operands respectively. The PUs, usingadder compressors, were applied to the ME architecture. The implemented architecture wasdescribed in VHDL and synthesized to FPGA and, with Leonardo Spectrum tool, to the TSMC0.18μm CMOS standard cell technology. Synthesis results indicate that the new QSDS-DIC archi-tecture reach the best performance result and enable gains of 12% in terms of processing rate. Thearchitecture can reach real time for full HDTV (1920x1080 pixels) in the worst case processing 65frames per second, and it can process 269 HDTV frames per second in the average case. |
publishDate |
2010 |
dc.date.issued.fl_str_mv |
2010 |
dc.date.accessioned.fl_str_mv |
2024-02-02T05:05:47Z |
dc.type.driver.fl_str_mv |
info:eu-repo/semantics/article info:eu-repo/semantics/other |
dc.type.status.fl_str_mv |
info:eu-repo/semantics/publishedVersion |
format |
article |
status_str |
publishedVersion |
dc.identifier.uri.fl_str_mv |
http://hdl.handle.net/10183/271367 |
dc.identifier.issn.pt_BR.fl_str_mv |
1807-1953 |
dc.identifier.nrb.pt_BR.fl_str_mv |
000784517 |
identifier_str_mv |
1807-1953 000784517 |
url |
http://hdl.handle.net/10183/271367 |
dc.language.iso.fl_str_mv |
eng |
language |
eng |
dc.relation.ispartof.pt_BR.fl_str_mv |
Journal of integrated circuits and systems. Vol. 5, n. 1 (Mar. 2010), p. 78-88 |
dc.rights.driver.fl_str_mv |
info:eu-repo/semantics/openAccess |
eu_rights_str_mv |
openAccess |
dc.format.none.fl_str_mv |
application/pdf |
dc.source.none.fl_str_mv |
reponame:Repositório Institucional da UFRGS instname:Universidade Federal do Rio Grande do Sul (UFRGS) instacron:UFRGS |
instname_str |
Universidade Federal do Rio Grande do Sul (UFRGS) |
instacron_str |
UFRGS |
institution |
UFRGS |
reponame_str |
Repositório Institucional da UFRGS |
collection |
Repositório Institucional da UFRGS |
bitstream.url.fl_str_mv |
http://www.lume.ufrgs.br/bitstream/10183/271367/2/000784517.pdf.txt http://www.lume.ufrgs.br/bitstream/10183/271367/1/000784517.pdf |
bitstream.checksum.fl_str_mv |
035dfe53ebfa99ad12ae26935a420227 96e24a8eee183a9b91d89a1afc9d1baa |
bitstream.checksumAlgorithm.fl_str_mv |
MD5 MD5 |
repository.name.fl_str_mv |
Repositório Institucional da UFRGS - Universidade Federal do Rio Grande do Sul (UFRGS) |
repository.mail.fl_str_mv |
|
_version_ |
1801225110261071872 |