Compact modelling and parameter extraction of nanoscale FinFETs

• Autor(a) principal: Leonhardt, Alessandra
• Data de Publicação: 2014
• Tipo de documento: Trabalho de conclusão de curso
• Idioma: eng
• Título da fonte: Repositório Institucional da UFRGS
• Texto Completo: http://hdl.handle.net/10183/110755
• topic: Microeletrônica; Mosfet; FinFETs; Compact models; Parameter extraction; MOSFET; BSIM-CMG; EKVDG; Effective channel length

This graduation work presents a study of FinFETs, compact models and their parameter extraction procedures, and also the results of parameter extractions of measured FinFET devices for different compact models, as well as other electrical parameters extracted from the transistors. The first part of this report will explain in detail the existing challenges to further scale the dimensions of the MOSFET device, such as short channel and parasitic effects, as well as large statistical device variations, that have become proeminent and assume a higher influence in the device behaviour. The FinFET architecture promises a better electrical behaviour in sub-22nm lengths, and will be discussed in detail. A large set of FinFET devices has been manufactured in the IMEC Institute, Belgium, and characterised in the PhD thesis of (FERREIRA, 2012) and is used throughout this work. The FinFET devices range from 10μm to 45nm of mask length, with fin thickness of 10nm, 15nm and 20nm. A compact model uses assumptions and simplifications to predict the electrical output characteristics of a device, while being computationally efficient. In this work, the EKV Double- Gate model, the BSIM-CMG and the PSP-DGFET will be studied, along with their parameter extraction procedures. Changes are proposed to the BSIM-CMG global parameter extraction in order to ensure that the parameters are consistent with the whole set of devices. The results obtained for the implemented parameter extractions are presented and discussed. Electrical parameters, such as series resistance and effective length have been extracted using different methodologies available in the literature. The extracted series resistance ranges from 500 to 300 , and the channel length reduction varies between 14nm and 16nm. The EKV Double-Gate model and parameter extraction has been implemented in MATLAB and the results show weaknesses in the model. The BSIM-CMG parameter extraction procedure was implemented in IC-CAP and shows an accurate fitting over a wide range of channel lengths using a single set of parameters, with error mean absolute around 20% in all operation regimes. Subjective analysis are also used to compare and demonstrate issues that the models and extraction procedures present.