A novel voltage-mode CMOS quaternary logic design
Autor(a) principal: | |
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Data de Publicação: | 2006 |
Outros Autores: | , |
Tipo de documento: | Artigo |
Idioma: | eng |
Título da fonte: | Repositório Institucional da UFRGS |
Texto Completo: | http://hdl.handle.net/10183/27584 |
Resumo: | This brief presents a novel kind of voltage-mode CMOS design that uses multiple threshold voltage transistors and three power supply lines to implement quaternary logic gates, showing lower power dissipation and using less area than the present voltage-mode quaternary circuits. Inverter, NMIN, and NMAX gates are simulated with the Spice tool using TSMC 0.18-μm technology. The proposed logic circuits overcome the limitations of previous implementations used for multiple-valued logic circuits, such as static power consumption and noise vulnerability. |
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Silva, Ricardo Cunha Gonçalves daBoudinov, Henri IvanovCarro, Luigi2011-01-28T05:59:11Z20060018-9383http://hdl.handle.net/10183/27584000565276This brief presents a novel kind of voltage-mode CMOS design that uses multiple threshold voltage transistors and three power supply lines to implement quaternary logic gates, showing lower power dissipation and using less area than the present voltage-mode quaternary circuits. Inverter, NMIN, and NMAX gates are simulated with the Spice tool using TSMC 0.18-μm technology. The proposed logic circuits overcome the limitations of previous implementations used for multiple-valued logic circuits, such as static power consumption and noise vulnerability.application/pdfengIEEE transactions on electron devices. New York. Vol. 53, n. 6 (June 2006), p. 1480-1483MicroeletrônicaInverterMultiple-valued logic (MVL) circuitsNMAXNMINVoltage-mode quaternaryCMOS desigA novel voltage-mode CMOS quaternary logic designEstrangeiroinfo:eu-repo/semantics/articleinfo:eu-repo/semantics/publishedVersioninfo:eu-repo/semantics/openAccessreponame:Repositório Institucional da UFRGSinstname:Universidade Federal do Rio Grande do Sul (UFRGS)instacron:UFRGSORIGINAL000565276.pdf000565276.pdfTexto completo (inglês)application/pdf162890http://www.lume.ufrgs.br/bitstream/10183/27584/1/000565276.pdf35c95837e44245f3e6d282ae512d46d0MD51TEXT000565276.pdf.txt000565276.pdf.txtExtracted Texttext/plain22374http://www.lume.ufrgs.br/bitstream/10183/27584/2/000565276.pdf.txtf7774679de1aca0abfe4effe1f976779MD52THUMBNAIL000565276.pdf.jpg000565276.pdf.jpgGenerated Thumbnailimage/jpeg2044http://www.lume.ufrgs.br/bitstream/10183/27584/3/000565276.pdf.jpge190fa1314672667634bc01bac95d7c0MD5310183/275842021-06-13 04:32:22.325031oai:www.lume.ufrgs.br:10183/27584Repositório de PublicaçõesPUBhttps://lume.ufrgs.br/oai/requestopendoar:2021-06-13T07:32:22Repositório Institucional da UFRGS - Universidade Federal do Rio Grande do Sul (UFRGS)false |
dc.title.pt_BR.fl_str_mv |
A novel voltage-mode CMOS quaternary logic design |
title |
A novel voltage-mode CMOS quaternary logic design |
spellingShingle |
A novel voltage-mode CMOS quaternary logic design Silva, Ricardo Cunha Gonçalves da Microeletrônica Inverter Multiple-valued logic (MVL) circuits NMAX NMIN Voltage-mode quaternary CMOS desig |
title_short |
A novel voltage-mode CMOS quaternary logic design |
title_full |
A novel voltage-mode CMOS quaternary logic design |
title_fullStr |
A novel voltage-mode CMOS quaternary logic design |
title_full_unstemmed |
A novel voltage-mode CMOS quaternary logic design |
title_sort |
A novel voltage-mode CMOS quaternary logic design |
author |
Silva, Ricardo Cunha Gonçalves da |
author_facet |
Silva, Ricardo Cunha Gonçalves da Boudinov, Henri Ivanov Carro, Luigi |
author_role |
author |
author2 |
Boudinov, Henri Ivanov Carro, Luigi |
author2_role |
author author |
dc.contributor.author.fl_str_mv |
Silva, Ricardo Cunha Gonçalves da Boudinov, Henri Ivanov Carro, Luigi |
dc.subject.por.fl_str_mv |
Microeletrônica |
topic |
Microeletrônica Inverter Multiple-valued logic (MVL) circuits NMAX NMIN Voltage-mode quaternary CMOS desig |
dc.subject.eng.fl_str_mv |
Inverter Multiple-valued logic (MVL) circuits NMAX NMIN Voltage-mode quaternary CMOS desig |
description |
This brief presents a novel kind of voltage-mode CMOS design that uses multiple threshold voltage transistors and three power supply lines to implement quaternary logic gates, showing lower power dissipation and using less area than the present voltage-mode quaternary circuits. Inverter, NMIN, and NMAX gates are simulated with the Spice tool using TSMC 0.18-μm technology. The proposed logic circuits overcome the limitations of previous implementations used for multiple-valued logic circuits, such as static power consumption and noise vulnerability. |
publishDate |
2006 |
dc.date.issued.fl_str_mv |
2006 |
dc.date.accessioned.fl_str_mv |
2011-01-28T05:59:11Z |
dc.type.driver.fl_str_mv |
Estrangeiro info:eu-repo/semantics/article |
dc.type.status.fl_str_mv |
info:eu-repo/semantics/publishedVersion |
format |
article |
status_str |
publishedVersion |
dc.identifier.uri.fl_str_mv |
http://hdl.handle.net/10183/27584 |
dc.identifier.issn.pt_BR.fl_str_mv |
0018-9383 |
dc.identifier.nrb.pt_BR.fl_str_mv |
000565276 |
identifier_str_mv |
0018-9383 000565276 |
url |
http://hdl.handle.net/10183/27584 |
dc.language.iso.fl_str_mv |
eng |
language |
eng |
dc.relation.ispartof.pt_BR.fl_str_mv |
IEEE transactions on electron devices. New York. Vol. 53, n. 6 (June 2006), p. 1480-1483 |
dc.rights.driver.fl_str_mv |
info:eu-repo/semantics/openAccess |
eu_rights_str_mv |
openAccess |
dc.format.none.fl_str_mv |
application/pdf |
dc.source.none.fl_str_mv |
reponame:Repositório Institucional da UFRGS instname:Universidade Federal do Rio Grande do Sul (UFRGS) instacron:UFRGS |
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UFRGS |
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UFRGS |
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Repositório Institucional da UFRGS |
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Repositório Institucional da UFRGS |
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