Specification and design of an ethernet interface soft ip
Autor(a) principal: | |
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Data de Publicação: | 2000 |
Outros Autores: | , , , |
Tipo de documento: | Artigo |
Idioma: | eng |
Título da fonte: | Repositório Institucional da UFRGS |
Texto Completo: | http://hdl.handle.net/10183/72564 |
Resumo: | The IP (Intellectual Property) for Ethernet Interface is a hardware module designed to execute the MAC (media access control) service on the Ethernet standard. The goal of this IP module is to provide an easy way to develop new devices with connection to an Ethernet LAN (Local Area Network). The standard protocols used make this IP module reusable for different designs with an interface to Ethernet LANs. The Ethernet Interface IP is described and simulated in VHDL. |
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Fragoso, Joao LeonardoCosta, Eduardo Antonio Cesar daRochol, JuergenBampi, SergioReis, Ricardo Augusto da Luz2013-06-19T01:43:32Z20000104-6500http://hdl.handle.net/10183/72564000270878The IP (Intellectual Property) for Ethernet Interface is a hardware module designed to execute the MAC (media access control) service on the Ethernet standard. The goal of this IP module is to provide an easy way to develop new devices with connection to an Ethernet LAN (Local Area Network). The standard protocols used make this IP module reusable for different designs with an interface to Ethernet LANs. The Ethernet Interface IP is described and simulated in VHDL.application/pdfengJournal of the Brazilian Computer Society. Rio de Janeiro. Vol. 6, n. 3 (apr. 2000), p. 5-12Redes : ComputadoresLanIPEthernet interfaceLocal area networkDesign with VHDLVLSI designSpecification and design of an ethernet interface soft ipinfo:eu-repo/semantics/articleinfo:eu-repo/semantics/otherinfo:eu-repo/semantics/publishedVersioninfo:eu-repo/semantics/openAccessreponame:Repositório Institucional da UFRGSinstname:Universidade Federal do Rio Grande do Sul (UFRGS)instacron:UFRGSORIGINAL000270878.pdf000270878.pdfTexto completo (inglês)application/pdf241890http://www.lume.ufrgs.br/bitstream/10183/72564/1/000270878.pdf86b6e295d13fe88ca5bc909e2f2eef9fMD51TEXT000270878.pdf.txt000270878.pdf.txtExtracted Texttext/plain18995http://www.lume.ufrgs.br/bitstream/10183/72564/2/000270878.pdf.txtfb629b0cb6ef7e9c8cfcc1375e9d1136MD52THUMBNAIL000270878.pdf.jpg000270878.pdf.jpgGenerated Thumbnailimage/jpeg1886http://www.lume.ufrgs.br/bitstream/10183/72564/3/000270878.pdf.jpgb15f70cd151082a9e0311038b096d94cMD5310183/725642018-10-16 09:32:57.574oai:www.lume.ufrgs.br:10183/72564Repositório de PublicaçõesPUBhttps://lume.ufrgs.br/oai/requestopendoar:2018-10-16T12:32:57Repositório Institucional da UFRGS - Universidade Federal do Rio Grande do Sul (UFRGS)false |
dc.title.pt_BR.fl_str_mv |
Specification and design of an ethernet interface soft ip |
title |
Specification and design of an ethernet interface soft ip |
spellingShingle |
Specification and design of an ethernet interface soft ip Fragoso, Joao Leonardo Redes : Computadores Lan IP Ethernet interface Local area network Design with VHDL VLSI design |
title_short |
Specification and design of an ethernet interface soft ip |
title_full |
Specification and design of an ethernet interface soft ip |
title_fullStr |
Specification and design of an ethernet interface soft ip |
title_full_unstemmed |
Specification and design of an ethernet interface soft ip |
title_sort |
Specification and design of an ethernet interface soft ip |
author |
Fragoso, Joao Leonardo |
author_facet |
Fragoso, Joao Leonardo Costa, Eduardo Antonio Cesar da Rochol, Juergen Bampi, Sergio Reis, Ricardo Augusto da Luz |
author_role |
author |
author2 |
Costa, Eduardo Antonio Cesar da Rochol, Juergen Bampi, Sergio Reis, Ricardo Augusto da Luz |
author2_role |
author author author author |
dc.contributor.author.fl_str_mv |
Fragoso, Joao Leonardo Costa, Eduardo Antonio Cesar da Rochol, Juergen Bampi, Sergio Reis, Ricardo Augusto da Luz |
dc.subject.por.fl_str_mv |
Redes : Computadores Lan IP |
topic |
Redes : Computadores Lan IP Ethernet interface Local area network Design with VHDL VLSI design |
dc.subject.eng.fl_str_mv |
Ethernet interface Local area network Design with VHDL VLSI design |
description |
The IP (Intellectual Property) for Ethernet Interface is a hardware module designed to execute the MAC (media access control) service on the Ethernet standard. The goal of this IP module is to provide an easy way to develop new devices with connection to an Ethernet LAN (Local Area Network). The standard protocols used make this IP module reusable for different designs with an interface to Ethernet LANs. The Ethernet Interface IP is described and simulated in VHDL. |
publishDate |
2000 |
dc.date.issued.fl_str_mv |
2000 |
dc.date.accessioned.fl_str_mv |
2013-06-19T01:43:32Z |
dc.type.driver.fl_str_mv |
info:eu-repo/semantics/article info:eu-repo/semantics/other |
dc.type.status.fl_str_mv |
info:eu-repo/semantics/publishedVersion |
format |
article |
status_str |
publishedVersion |
dc.identifier.uri.fl_str_mv |
http://hdl.handle.net/10183/72564 |
dc.identifier.issn.pt_BR.fl_str_mv |
0104-6500 |
dc.identifier.nrb.pt_BR.fl_str_mv |
000270878 |
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0104-6500 000270878 |
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http://hdl.handle.net/10183/72564 |
dc.language.iso.fl_str_mv |
eng |
language |
eng |
dc.relation.ispartof.pt_BR.fl_str_mv |
Journal of the Brazilian Computer Society. Rio de Janeiro. Vol. 6, n. 3 (apr. 2000), p. 5-12 |
dc.rights.driver.fl_str_mv |
info:eu-repo/semantics/openAccess |
eu_rights_str_mv |
openAccess |
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application/pdf |
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reponame:Repositório Institucional da UFRGS instname:Universidade Federal do Rio Grande do Sul (UFRGS) instacron:UFRGS |
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UFRGS |
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Repositório Institucional da UFRGS |
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Repositório Institucional da UFRGS |
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