Contribuição para o estudo do embarque de uma rede neural artificial em field programmable gate array (FPGA)

• Autor(a) principal: Silva, Carlos Alberto de Albuquerque
• Data de Publicação: 2010
• Tipo de documento: Dissertação
• Idioma: por
• Título da fonte: Repositório Institucional da UFRN
• Texto Completo: https://repositorio.ufrn.br/jspui/handle/123456789/15340
• topic: Computação reconfigurável; Redes neurais artificiais; FPGA; VHDL; Hardware; Aritmética ponto fixo; Reconfigurable computing; Artificial neural network; FPGA; VHDL; Hardware; Arithmetic fixed point; CNPQ::ENGENHARIAS::ENGENHARIA ELETRICA

This study shows the implementation and the embedding of an Artificial Neural Network (ANN) in hardware, or in a programmable device, as a field programmable gate array (FPGA). This work allowed the exploration of different implementations, described in VHDL, of multilayer perceptrons ANN. Due to the parallelism inherent to ANNs, there are disadvantages in software implementations due to the sequential nature of the Von Neumann architectures. As an alternative to this problem, there is a hardware implementation that allows to exploit all the parallelism implicit in this model. Currently, there is an increase in use of FPGAs as a platform to implement neural networks in hardware, exploiting the high processing power, low cost, ease of programming and ability to reconfigure the circuit, allowing the network to adapt to different applications. Given this context, the aim is to develop arrays of neural networks in hardware, a flexible architecture, in which it is possible to add or remove neurons, and mainly, modify the network topology, in order to enable a modular network of fixed-point arithmetic in a FPGA. Five synthesis of VHDL descriptions were produced: two for the neuron with one or two entrances, and three different architectures of ANN. The descriptions of the used architectures became very modular, easily allowing the increase or decrease of the number of neurons. As a result, some complete neural networks were implemented in FPGA, in fixed-point arithmetic, with a high-capacity parallel processing