Implementation of 3-D multiple linear regression in hardware using the xilinx spartan-3AN FPGA

Detalhes bibliográficos
Autor(a) principal: Grout, Ian
Data de Publicação: 2019
Outros Autores: Ferreira, Willian De Assis Pedrobon [UNESP], Silva, Alexandre Cesar Rodrigues Da [UNESP]
Tipo de documento: Artigo de conferência
Idioma: eng
Título da fonte: Repositório Institucional da UNESP
Texto Completo: http://dx.doi.org/10.1109/ECTI-CON47248.2019.8955155
http://hdl.handle.net/11449/232965
Resumo: In this paper, a linear regression algorithm implementation in hardware using the Field Programmable Gate Array (FPGA) is presented. A two-dimensional (2-D) simple linear regression aims to develop a linear equation of two variables based on observed data values in two dimensions. A more complex problem that this considered in this paper is the three-dimensional (3-D) multiple linear regression that approximates a linear equation of three variables based on a set of observed data points in three dimensions. The algorithm was initially modelled and verified using Python, NumPy and Matplotlib. The linear regression equation was then translated to hardware using a VHDL description of the algorithm targeting the Xilinx Spartan-3AN FPGA. In this paper, the design and simulation of the algorithm based on using the available hardware resources within the FPGA are introduced and discussed.
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spelling Implementation of 3-D multiple linear regression in hardware using the xilinx spartan-3AN FPGAFPGAHardwareLinear regressionMachine learningVHDLIn this paper, a linear regression algorithm implementation in hardware using the Field Programmable Gate Array (FPGA) is presented. A two-dimensional (2-D) simple linear regression aims to develop a linear equation of two variables based on observed data values in two dimensions. A more complex problem that this considered in this paper is the three-dimensional (3-D) multiple linear regression that approximates a linear equation of three variables based on a set of observed data points in three dimensions. The algorithm was initially modelled and verified using Python, NumPy and Matplotlib. The linear regression equation was then translated to hardware using a VHDL description of the algorithm targeting the Xilinx Spartan-3AN FPGA. In this paper, the design and simulation of the algorithm based on using the available hardware resources within the FPGA are introduced and discussed.University of Limerick Department of Electronic and Computer EngineeringUniversidade Estadual Paulista Faculdade de Engenharia Ilha SolteiraUniversidade Estadual Paulista Faculdade de Engenharia Ilha SolteiraUniversity of LimerickUniversidade Estadual Paulista (UNESP)Grout, IanFerreira, Willian De Assis Pedrobon [UNESP]Silva, Alexandre Cesar Rodrigues Da [UNESP]2022-04-30T22:43:07Z2022-04-30T22:43:07Z2019-07-01info:eu-repo/semantics/publishedVersioninfo:eu-repo/semantics/conferenceObject171-174http://dx.doi.org/10.1109/ECTI-CON47248.2019.8955155Proceedings of the 16th International Conference on Electrical Engineering/Electronics, Computer, Telecommunications and Information Technology, ECTI-CON 2019, p. 171-174.http://hdl.handle.net/11449/23296510.1109/ECTI-CON47248.2019.89551552-s2.0-85078859132Scopusreponame:Repositório Institucional da UNESPinstname:Universidade Estadual Paulista (UNESP)instacron:UNESPengProceedings of the 16th International Conference on Electrical Engineering/Electronics, Computer, Telecommunications and Information Technology, ECTI-CON 2019info:eu-repo/semantics/openAccess2024-07-04T19:11:17Zoai:repositorio.unesp.br:11449/232965Repositório InstitucionalPUBhttp://repositorio.unesp.br/oai/requestopendoar:29462024-08-05T14:33:41.181868Repositório Institucional da UNESP - Universidade Estadual Paulista (UNESP)false
dc.title.none.fl_str_mv Implementation of 3-D multiple linear regression in hardware using the xilinx spartan-3AN FPGA
title Implementation of 3-D multiple linear regression in hardware using the xilinx spartan-3AN FPGA
spellingShingle Implementation of 3-D multiple linear regression in hardware using the xilinx spartan-3AN FPGA
Grout, Ian
FPGA
Hardware
Linear regression
Machine learning
VHDL
title_short Implementation of 3-D multiple linear regression in hardware using the xilinx spartan-3AN FPGA
title_full Implementation of 3-D multiple linear regression in hardware using the xilinx spartan-3AN FPGA
title_fullStr Implementation of 3-D multiple linear regression in hardware using the xilinx spartan-3AN FPGA
title_full_unstemmed Implementation of 3-D multiple linear regression in hardware using the xilinx spartan-3AN FPGA
title_sort Implementation of 3-D multiple linear regression in hardware using the xilinx spartan-3AN FPGA
author Grout, Ian
author_facet Grout, Ian
Ferreira, Willian De Assis Pedrobon [UNESP]
Silva, Alexandre Cesar Rodrigues Da [UNESP]
author_role author
author2 Ferreira, Willian De Assis Pedrobon [UNESP]
Silva, Alexandre Cesar Rodrigues Da [UNESP]
author2_role author
author
dc.contributor.none.fl_str_mv University of Limerick
Universidade Estadual Paulista (UNESP)
dc.contributor.author.fl_str_mv Grout, Ian
Ferreira, Willian De Assis Pedrobon [UNESP]
Silva, Alexandre Cesar Rodrigues Da [UNESP]
dc.subject.por.fl_str_mv FPGA
Hardware
Linear regression
Machine learning
VHDL
topic FPGA
Hardware
Linear regression
Machine learning
VHDL
description In this paper, a linear regression algorithm implementation in hardware using the Field Programmable Gate Array (FPGA) is presented. A two-dimensional (2-D) simple linear regression aims to develop a linear equation of two variables based on observed data values in two dimensions. A more complex problem that this considered in this paper is the three-dimensional (3-D) multiple linear regression that approximates a linear equation of three variables based on a set of observed data points in three dimensions. The algorithm was initially modelled and verified using Python, NumPy and Matplotlib. The linear regression equation was then translated to hardware using a VHDL description of the algorithm targeting the Xilinx Spartan-3AN FPGA. In this paper, the design and simulation of the algorithm based on using the available hardware resources within the FPGA are introduced and discussed.
publishDate 2019
dc.date.none.fl_str_mv 2019-07-01
2022-04-30T22:43:07Z
2022-04-30T22:43:07Z
dc.type.status.fl_str_mv info:eu-repo/semantics/publishedVersion
dc.type.driver.fl_str_mv info:eu-repo/semantics/conferenceObject
format conferenceObject
status_str publishedVersion
dc.identifier.uri.fl_str_mv http://dx.doi.org/10.1109/ECTI-CON47248.2019.8955155
Proceedings of the 16th International Conference on Electrical Engineering/Electronics, Computer, Telecommunications and Information Technology, ECTI-CON 2019, p. 171-174.
http://hdl.handle.net/11449/232965
10.1109/ECTI-CON47248.2019.8955155
2-s2.0-85078859132
url http://dx.doi.org/10.1109/ECTI-CON47248.2019.8955155
http://hdl.handle.net/11449/232965
identifier_str_mv Proceedings of the 16th International Conference on Electrical Engineering/Electronics, Computer, Telecommunications and Information Technology, ECTI-CON 2019, p. 171-174.
10.1109/ECTI-CON47248.2019.8955155
2-s2.0-85078859132
dc.language.iso.fl_str_mv eng
language eng
dc.relation.none.fl_str_mv Proceedings of the 16th International Conference on Electrical Engineering/Electronics, Computer, Telecommunications and Information Technology, ECTI-CON 2019
dc.rights.driver.fl_str_mv info:eu-repo/semantics/openAccess
eu_rights_str_mv openAccess
dc.format.none.fl_str_mv 171-174
dc.source.none.fl_str_mv Scopus
reponame:Repositório Institucional da UNESP
instname:Universidade Estadual Paulista (UNESP)
instacron:UNESP
instname_str Universidade Estadual Paulista (UNESP)
instacron_str UNESP
institution UNESP
reponame_str Repositório Institucional da UNESP
collection Repositório Institucional da UNESP
repository.name.fl_str_mv Repositório Institucional da UNESP - Universidade Estadual Paulista (UNESP)
repository.mail.fl_str_mv
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