Heurísticas para a geração de arquiteturas reconfiguráveis em arranjos bidimensionais

• Autor(a) principal: Teixeira, Tiago Aparecido
• Data de Publicação: 2009
• Tipo de documento: Dissertação
• Idioma: por
• Título da fonte: LOCUS Repositório Institucional da UFV
• Texto Completo: http://locus.ufv.br/handle/123456789/2595
• topic: Arquiteturas reconfiguráveis; Heurísticas; Arranjos de grão grosso; Reconfigurable architectures; Heuristics; Coarse-grained arrays; CNPQ::CIENCIAS EXATAS E DA TERRA::CIENCIA DA COMPUTACAO

Coarse-grained reconfigurable architecture appears as an alternative solution to reduce the design time, the routing and placement complexity, the reconfiguration time, and the reconfiguration memory, to design high performance and low power embedded system. However, the design space is too wide and it needs new explorations tools. This work proposes an tool of the automatic exploration of design space of the topologies, to be the foccus based in heuristics (Genetic Algorithms, Simulated Annealing and Path Relinking) and schedule algorithms (ASAP and ALAP) to see reconfigurable architecture in arrays with regular patterns and scalable of the interconnection. To validate this tool, a set of multimedia applications, from the set of clusters Media bench and algorithms for signal processing (FIR, DCT etc.) was used in the evaluation of the generated architectures. The criteria for cost take into account the number of connections after the mapping, the critical path and the time to search for solutions. The experimental results showed that the generated architecture can reduce by almost 20% the cost of connections when compared to the topology 0_1_hop, identified by other studies as the most appropriate.