Tunnel-FET Evolution and Applications for Analog Circuits

• Autor(a) principal: Agopian, Paula G. D. [UNESP]
• Data de Publicação: 2022
• Outros Autores: Martino, Joao A., Simoen, Eddy, Rooyackers, Rita, Claeys, Cor
• Tipo de documento: Artigo
• Idioma: eng
• Título da fonte: Repositório Institucional da UNESP
• Texto Completo: http://dx.doi.org/10.29292/jics.v17i2.631; http://hdl.handle.net/11449/246570
• topic: digital and analog performance; geometries; new materials; TFET

In this work different generations of field effect tunneling transistor (TFET) are evaluated through DC digital and analog figures of merits. For TFET devices the main digital figure of merit is the subthreshold slope (SS), while for analog application the intrinsic voltage gain (AV) is the most important one. For the early generations, that are based on silicon, the SS does not reach values smaller than 60mV/dec at room temper-ature, however, the AV reaches values up to 80 dB, showing to be promising for analog applications. As the TFETs were being optimized for digital applications and consequently presenting better switching performance, the intrinsic voltage gain moves in the opposite direction. This opposite trend is related to which transport mechanism is predominant for each type of device. While III-V TFETs are more dependent on Band to Band Tunneling (BTBT), silicon devices are more relying on Trap-As-sisted Tunneling (TAT). While BTBT allows for faster switch-ing, TAT is less dependent on the drain electric field, so the for-mer favors SS while the latter favors AV. Based on the good analog behavior of silicon channel TFETs, a two-stage operational transconductance amplifier (OTA) was designed with different TFET technologies and the compared results were discussed.