Using multiple abstraction levels to speedup an MPSoC virtual platform simulator

• Autor(a) principal: Moreira, João
• Data de Publicação: 2011
• Outros Autores: Klein, Felipe, Baldassin, Alexandro [UNESP], Centoducatte, Paulo, Azevedo, Rodolfo, Rigo, Sandro
• Tipo de documento: Artigo de conferência
• Idioma: eng
• Título da fonte: Repositório Institucional da UNESP
• Texto Completo: http://dx.doi.org/10.1109/RSP.2011.5929982; http://hdl.handle.net/11449/72565
• topic: Abstraction level; Communication mechanisms; Cycle accurate; Design space exploration; Fast simulation; Hybrid platform; Instruction set simulators; Power estimations; Simulation platform; Standard deviation; Virtual platform; Embedded systems; Multiprocessing systems; Software design; Space platforms; Space research; Specifications; Verification; Computer software

Virtual platforms are of paramount importance for design space exploration and their usage in early software development and verification is crucial. In particular, enabling accurate and fast simulation is specially useful, but such features are usually conflicting and tradeoffs have to be made. In this paper we describe how we integrated TLM communication mechanisms into a state-of-the-art, cycle-accurate, MPSoC simulation platform. More specifically, we show how we adapted ArchC fast functional instruction set simulators to the MPARM platform in order to achieve both fast simulation speed and accuracy. Our implementation led to a much faster hybrid platform, reaching speedups of up to 2.9 and 2.1x on average with negligible impact on power estimation accuracy (average 3.26% and 2.25% of standard deviation). © 2011 IEEE.