Synthesis and Optimization of Majority Expressions through a Mathematical Model
Autor(a) principal: | |
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Data de Publicação: | 2020 |
Outros Autores: | , , , |
Tipo de documento: | Artigo de conferência |
Idioma: | eng |
Título da fonte: | Repositório Institucional da UNESP |
Texto Completo: | http://hdl.handle.net/11449/210130 |
Resumo: | In this paper, the 3MS (Majority Math Model Solver) algorithm is proposed for use in the optimization of majority logic circuits. The new proposed algorithm receives a sequence of binary numbers as input, representing truth tables with a minimum of 3 and a maximum of 8 variables, and returns an optimized majority function that covers the same minterms. Key in this approach is the formulation of constraints that encode a majority logic problem into a mathematical optimization problem. The resulting set of constraints is then applied to an optimization solver and the results are translated into the output majority function. As cost criteria the minimization of levels is prioritized, followed by the minimization of gates, inverters and gate inputs. The 3MS algorithm was evaluated based on a comparison with the state-of-the-art exact synthesis for majorityof-three networks, which considers the number of levels and gates as cost criteria. Since the 3MS considers two additional cost criterias, the goal of the algorithm is to generate functions that are also exact in relation to the number of levels and gates, but uses fewer inverters and gate inputs. Simulation studies have shown that the 3MS is able to further improve 79% of all 77,292 compared functions, and achieves equal results for the remaining 21%. |
id |
UNSP_255b0c3c18a1fc31fc42d2399b123095 |
---|---|
oai_identifier_str |
oai:repositorio.unesp.br:11449/210130 |
network_acronym_str |
UNSP |
network_name_str |
Repositório Institucional da UNESP |
repository_id_str |
2946 |
spelling |
Synthesis and Optimization of Majority Expressions through a Mathematical Modelmajority logicprimitive functionslogic synthesisoptimization solvermathematical modelIn this paper, the 3MS (Majority Math Model Solver) algorithm is proposed for use in the optimization of majority logic circuits. The new proposed algorithm receives a sequence of binary numbers as input, representing truth tables with a minimum of 3 and a maximum of 8 variables, and returns an optimized majority function that covers the same minterms. Key in this approach is the formulation of constraints that encode a majority logic problem into a mathematical optimization problem. The resulting set of constraints is then applied to an optimization solver and the results are translated into the output majority function. As cost criteria the minimization of levels is prioritized, followed by the minimization of gates, inverters and gate inputs. The 3MS algorithm was evaluated based on a comparison with the state-of-the-art exact synthesis for majorityof-three networks, which considers the number of levels and gates as cost criteria. Since the 3MS considers two additional cost criterias, the goal of the algorithm is to generate functions that are also exact in relation to the number of levels and gates, but uses fewer inverters and gate inputs. Simulation studies have shown that the 3MS is able to further improve 79% of all 77,292 compared functions, and achieves equal results for the remaining 21%.Coordenação de Aperfeiçoamento de Pessoal de Nível Superior (CAPES)Univ Estadual Paulista, FEIS, Dept Elect Engn, Ilha Solteira, BrazilUniv Limerick, Dept Elect & Comp Engn, Limerick, IrelandUniv Estadual Paulista, FEIS, Dept Elect Engn, Ilha Solteira, BrazilCAPES: 001IeeeUniversidade Estadual Paulista (Unesp)Univ LimerickFerraz, Evandro C. [UNESP]Jose, V. O. Junior [UNESP]Grout, IanSilva, Alexandre C. R. da [UNESP]IEEE2021-06-25T12:40:37Z2021-06-25T12:40:37Z2020-01-01info:eu-repo/semantics/publishedVersioninfo:eu-repo/semantics/conferenceObject633rd Symposium On Integrated Circuits And Systems Design (sbcci 2020). New York: Ieee, 6 p., 2020.http://hdl.handle.net/11449/210130WOS:000629184200014Web of Sciencereponame:Repositório Institucional da UNESPinstname:Universidade Estadual Paulista (UNESP)instacron:UNESPeng33rd Symposium On Integrated Circuits And Systems Design (sbcci 2020)info:eu-repo/semantics/openAccess2024-07-04T19:11:28Zoai:repositorio.unesp.br:11449/210130Repositório InstitucionalPUBhttp://repositorio.unesp.br/oai/requestopendoar:29462024-08-05T16:30:09.228146Repositório Institucional da UNESP - Universidade Estadual Paulista (UNESP)false |
dc.title.none.fl_str_mv |
Synthesis and Optimization of Majority Expressions through a Mathematical Model |
title |
Synthesis and Optimization of Majority Expressions through a Mathematical Model |
spellingShingle |
Synthesis and Optimization of Majority Expressions through a Mathematical Model Ferraz, Evandro C. [UNESP] majority logic primitive functions logic synthesis optimization solver mathematical model |
title_short |
Synthesis and Optimization of Majority Expressions through a Mathematical Model |
title_full |
Synthesis and Optimization of Majority Expressions through a Mathematical Model |
title_fullStr |
Synthesis and Optimization of Majority Expressions through a Mathematical Model |
title_full_unstemmed |
Synthesis and Optimization of Majority Expressions through a Mathematical Model |
title_sort |
Synthesis and Optimization of Majority Expressions through a Mathematical Model |
author |
Ferraz, Evandro C. [UNESP] |
author_facet |
Ferraz, Evandro C. [UNESP] Jose, V. O. Junior [UNESP] Grout, Ian Silva, Alexandre C. R. da [UNESP] IEEE |
author_role |
author |
author2 |
Jose, V. O. Junior [UNESP] Grout, Ian Silva, Alexandre C. R. da [UNESP] IEEE |
author2_role |
author author author author |
dc.contributor.none.fl_str_mv |
Universidade Estadual Paulista (Unesp) Univ Limerick |
dc.contributor.author.fl_str_mv |
Ferraz, Evandro C. [UNESP] Jose, V. O. Junior [UNESP] Grout, Ian Silva, Alexandre C. R. da [UNESP] IEEE |
dc.subject.por.fl_str_mv |
majority logic primitive functions logic synthesis optimization solver mathematical model |
topic |
majority logic primitive functions logic synthesis optimization solver mathematical model |
description |
In this paper, the 3MS (Majority Math Model Solver) algorithm is proposed for use in the optimization of majority logic circuits. The new proposed algorithm receives a sequence of binary numbers as input, representing truth tables with a minimum of 3 and a maximum of 8 variables, and returns an optimized majority function that covers the same minterms. Key in this approach is the formulation of constraints that encode a majority logic problem into a mathematical optimization problem. The resulting set of constraints is then applied to an optimization solver and the results are translated into the output majority function. As cost criteria the minimization of levels is prioritized, followed by the minimization of gates, inverters and gate inputs. The 3MS algorithm was evaluated based on a comparison with the state-of-the-art exact synthesis for majorityof-three networks, which considers the number of levels and gates as cost criteria. Since the 3MS considers two additional cost criterias, the goal of the algorithm is to generate functions that are also exact in relation to the number of levels and gates, but uses fewer inverters and gate inputs. Simulation studies have shown that the 3MS is able to further improve 79% of all 77,292 compared functions, and achieves equal results for the remaining 21%. |
publishDate |
2020 |
dc.date.none.fl_str_mv |
2020-01-01 2021-06-25T12:40:37Z 2021-06-25T12:40:37Z |
dc.type.status.fl_str_mv |
info:eu-repo/semantics/publishedVersion |
dc.type.driver.fl_str_mv |
info:eu-repo/semantics/conferenceObject |
format |
conferenceObject |
status_str |
publishedVersion |
dc.identifier.uri.fl_str_mv |
33rd Symposium On Integrated Circuits And Systems Design (sbcci 2020). New York: Ieee, 6 p., 2020. http://hdl.handle.net/11449/210130 WOS:000629184200014 |
identifier_str_mv |
33rd Symposium On Integrated Circuits And Systems Design (sbcci 2020). New York: Ieee, 6 p., 2020. WOS:000629184200014 |
url |
http://hdl.handle.net/11449/210130 |
dc.language.iso.fl_str_mv |
eng |
language |
eng |
dc.relation.none.fl_str_mv |
33rd Symposium On Integrated Circuits And Systems Design (sbcci 2020) |
dc.rights.driver.fl_str_mv |
info:eu-repo/semantics/openAccess |
eu_rights_str_mv |
openAccess |
dc.format.none.fl_str_mv |
6 |
dc.publisher.none.fl_str_mv |
Ieee |
publisher.none.fl_str_mv |
Ieee |
dc.source.none.fl_str_mv |
Web of Science reponame:Repositório Institucional da UNESP instname:Universidade Estadual Paulista (UNESP) instacron:UNESP |
instname_str |
Universidade Estadual Paulista (UNESP) |
instacron_str |
UNESP |
institution |
UNESP |
reponame_str |
Repositório Institucional da UNESP |
collection |
Repositório Institucional da UNESP |
repository.name.fl_str_mv |
Repositório Institucional da UNESP - Universidade Estadual Paulista (UNESP) |
repository.mail.fl_str_mv |
|
_version_ |
1808128661707030528 |