Synthesis and Optimization of Majority Expressions through a Mathematical Model
Autor(a) principal: | |
---|---|
Data de Publicação: | 2020 |
Outros Autores: | , , |
Tipo de documento: | Artigo de conferência |
Idioma: | eng |
Título da fonte: | Repositório Institucional da UNESP |
Texto Completo: | http://dx.doi.org/10.1109/SBCCI50935.2020.9189906 http://hdl.handle.net/11449/228865 |
Resumo: | In this paper, the 3MS (Majority Math Model Solver) algorithm is proposed for use in the optimization of majority logic circuits. The new proposed algorithm receives a sequence of binary numbers as input, representing truth tables with a minimum of 3 and a maximum of 8 variables, and returns an optimized majority function that covers the same minterms. Key in this approach is the formulation of constraints that encode a majority logic problem into a mathematical optimization problem. The resulting set of constraints is then applied to an optimization solver and the results are translated into the output majority function. As cost criteria the minimization of levels is prioritized, followed by the minimization of gates, inverters and gate inputs. The 3MS algorithm was evaluated based on a comparison with the state-of-the-art exact synthesis for majority-of-three networks, which considers the number of levels and gates as cost criteria. Since the 3MS considers two additional cost criterias, the goal of the algorithm is to generate functions that are also exact in relation to the number of levels and gates, but uses fewer inverters and gate inputs. Simulation studies have shown that the 3MS is able to further improve 79% of all 77,292 compared functions, and achieves equal results for the remaining 21%. |
id |
UNSP_e85719896a4b72fdcf94ee43185f724a |
---|---|
oai_identifier_str |
oai:repositorio.unesp.br:11449/228865 |
network_acronym_str |
UNSP |
network_name_str |
Repositório Institucional da UNESP |
repository_id_str |
2946 |
spelling |
Synthesis and Optimization of Majority Expressions through a Mathematical Modellogic synthesismajority logicmathematical modeloptimization solverprimitive functionsIn this paper, the 3MS (Majority Math Model Solver) algorithm is proposed for use in the optimization of majority logic circuits. The new proposed algorithm receives a sequence of binary numbers as input, representing truth tables with a minimum of 3 and a maximum of 8 variables, and returns an optimized majority function that covers the same minterms. Key in this approach is the formulation of constraints that encode a majority logic problem into a mathematical optimization problem. The resulting set of constraints is then applied to an optimization solver and the results are translated into the output majority function. As cost criteria the minimization of levels is prioritized, followed by the minimization of gates, inverters and gate inputs. The 3MS algorithm was evaluated based on a comparison with the state-of-the-art exact synthesis for majority-of-three networks, which considers the number of levels and gates as cost criteria. Since the 3MS considers two additional cost criterias, the goal of the algorithm is to generate functions that are also exact in relation to the number of levels and gates, but uses fewer inverters and gate inputs. Simulation studies have shown that the 3MS is able to further improve 79% of all 77,292 compared functions, and achieves equal results for the remaining 21%.FEIS - Univ. Estadual Paulista Dept. of Electrical EngineeringUniversity of Limerick Dept. of Electronic and Computer EngineeringFEIS - Univ. Estadual Paulista Dept. of Electrical EngineeringUniversidade Estadual Paulista (UNESP)Dept. of Electronic and Computer EngineeringFerraz, Evandro C. [UNESP]Junior, Jose V. O. [UNESP]Grout, IanDa Silva, Alexandre C. R. [UNESP]2022-04-29T08:29:03Z2022-04-29T08:29:03Z2020-08-01info:eu-repo/semantics/publishedVersioninfo:eu-repo/semantics/conferenceObjecthttp://dx.doi.org/10.1109/SBCCI50935.2020.9189906Proceedings - 33rd Symposium on Integrated Circuits and Systems Design, SBCCI 2020.http://hdl.handle.net/11449/22886510.1109/SBCCI50935.2020.91899062-s2.0-85093818195Scopusreponame:Repositório Institucional da UNESPinstname:Universidade Estadual Paulista (UNESP)instacron:UNESPengProceedings - 33rd Symposium on Integrated Circuits and Systems Design, SBCCI 2020info:eu-repo/semantics/openAccess2024-07-04T19:11:33Zoai:repositorio.unesp.br:11449/228865Repositório InstitucionalPUBhttp://repositorio.unesp.br/oai/requestopendoar:29462024-08-05T17:00:05.227691Repositório Institucional da UNESP - Universidade Estadual Paulista (UNESP)false |
dc.title.none.fl_str_mv |
Synthesis and Optimization of Majority Expressions through a Mathematical Model |
title |
Synthesis and Optimization of Majority Expressions through a Mathematical Model |
spellingShingle |
Synthesis and Optimization of Majority Expressions through a Mathematical Model Ferraz, Evandro C. [UNESP] logic synthesis majority logic mathematical model optimization solver primitive functions |
title_short |
Synthesis and Optimization of Majority Expressions through a Mathematical Model |
title_full |
Synthesis and Optimization of Majority Expressions through a Mathematical Model |
title_fullStr |
Synthesis and Optimization of Majority Expressions through a Mathematical Model |
title_full_unstemmed |
Synthesis and Optimization of Majority Expressions through a Mathematical Model |
title_sort |
Synthesis and Optimization of Majority Expressions through a Mathematical Model |
author |
Ferraz, Evandro C. [UNESP] |
author_facet |
Ferraz, Evandro C. [UNESP] Junior, Jose V. O. [UNESP] Grout, Ian Da Silva, Alexandre C. R. [UNESP] |
author_role |
author |
author2 |
Junior, Jose V. O. [UNESP] Grout, Ian Da Silva, Alexandre C. R. [UNESP] |
author2_role |
author author author |
dc.contributor.none.fl_str_mv |
Universidade Estadual Paulista (UNESP) Dept. of Electronic and Computer Engineering |
dc.contributor.author.fl_str_mv |
Ferraz, Evandro C. [UNESP] Junior, Jose V. O. [UNESP] Grout, Ian Da Silva, Alexandre C. R. [UNESP] |
dc.subject.por.fl_str_mv |
logic synthesis majority logic mathematical model optimization solver primitive functions |
topic |
logic synthesis majority logic mathematical model optimization solver primitive functions |
description |
In this paper, the 3MS (Majority Math Model Solver) algorithm is proposed for use in the optimization of majority logic circuits. The new proposed algorithm receives a sequence of binary numbers as input, representing truth tables with a minimum of 3 and a maximum of 8 variables, and returns an optimized majority function that covers the same minterms. Key in this approach is the formulation of constraints that encode a majority logic problem into a mathematical optimization problem. The resulting set of constraints is then applied to an optimization solver and the results are translated into the output majority function. As cost criteria the minimization of levels is prioritized, followed by the minimization of gates, inverters and gate inputs. The 3MS algorithm was evaluated based on a comparison with the state-of-the-art exact synthesis for majority-of-three networks, which considers the number of levels and gates as cost criteria. Since the 3MS considers two additional cost criterias, the goal of the algorithm is to generate functions that are also exact in relation to the number of levels and gates, but uses fewer inverters and gate inputs. Simulation studies have shown that the 3MS is able to further improve 79% of all 77,292 compared functions, and achieves equal results for the remaining 21%. |
publishDate |
2020 |
dc.date.none.fl_str_mv |
2020-08-01 2022-04-29T08:29:03Z 2022-04-29T08:29:03Z |
dc.type.status.fl_str_mv |
info:eu-repo/semantics/publishedVersion |
dc.type.driver.fl_str_mv |
info:eu-repo/semantics/conferenceObject |
format |
conferenceObject |
status_str |
publishedVersion |
dc.identifier.uri.fl_str_mv |
http://dx.doi.org/10.1109/SBCCI50935.2020.9189906 Proceedings - 33rd Symposium on Integrated Circuits and Systems Design, SBCCI 2020. http://hdl.handle.net/11449/228865 10.1109/SBCCI50935.2020.9189906 2-s2.0-85093818195 |
url |
http://dx.doi.org/10.1109/SBCCI50935.2020.9189906 http://hdl.handle.net/11449/228865 |
identifier_str_mv |
Proceedings - 33rd Symposium on Integrated Circuits and Systems Design, SBCCI 2020. 10.1109/SBCCI50935.2020.9189906 2-s2.0-85093818195 |
dc.language.iso.fl_str_mv |
eng |
language |
eng |
dc.relation.none.fl_str_mv |
Proceedings - 33rd Symposium on Integrated Circuits and Systems Design, SBCCI 2020 |
dc.rights.driver.fl_str_mv |
info:eu-repo/semantics/openAccess |
eu_rights_str_mv |
openAccess |
dc.source.none.fl_str_mv |
Scopus reponame:Repositório Institucional da UNESP instname:Universidade Estadual Paulista (UNESP) instacron:UNESP |
instname_str |
Universidade Estadual Paulista (UNESP) |
instacron_str |
UNESP |
institution |
UNESP |
reponame_str |
Repositório Institucional da UNESP |
collection |
Repositório Institucional da UNESP |
repository.name.fl_str_mv |
Repositório Institucional da UNESP - Universidade Estadual Paulista (UNESP) |
repository.mail.fl_str_mv |
|
_version_ |
1808128734629199872 |