Comparative analysis of the intrinsic voltage gain and unit gain frequency between SOI and bulk FinFETs up to high temperatures

Detalhes bibliográficos
Autor(a) principal: Oliveira, Alberto Vinicius de
Data de Publicação: 2016
Outros Autores: Agopian, Paula Ghedini Der [UNESP], Martino, Joao Antonio, Simoen, Eddy, Claeys, Cor, Collaert, Nadine, Thean, Aaron
Tipo de documento: Artigo
Idioma: eng
Título da fonte: Repositório Institucional da UNESP
Texto Completo: http://dx.doi.org/10.1016/j.sse.2016.05.004
http://hdl.handle.net/11449/168671
Resumo: This paper presents an experimental analysis of the analog application figures of merit: the intrinsic voltage gain (AV) and unit gain frequency, focusing on the performance comparison between silicon triple gate pFinFET devices, which were processed on both Si and Silicon-On-Insulator (SOI) substrates. The high temperature (from 25 °C to 150 °C) influence and different channel lengths and fin widths were also taken into account. While the temperature impact on the intrinsic voltage gain (AV) is limited, the unit gain frequency was strongly affected due to the carrier mobility degradation at higher temperatures, for both p- and n-type FinFET structures. In addition, the pFinFETs showed slightly larger AV values compared to the n-type counterparts, whereby the bulk FinFETs presented a higher dispersion than the SOI FinFETs.
id UNSP_399ca06cf16f828612ab2ca546550a7d
oai_identifier_str oai:repositorio.unesp.br:11449/168671
network_acronym_str UNSP
network_name_str Repositório Institucional da UNESP
repository_id_str 2946
spelling Comparative analysis of the intrinsic voltage gain and unit gain frequency between SOI and bulk FinFETs up to high temperaturesAnalog parametersBulk pFinFETHigh temperatureSOI pFinFETThis paper presents an experimental analysis of the analog application figures of merit: the intrinsic voltage gain (AV) and unit gain frequency, focusing on the performance comparison between silicon triple gate pFinFET devices, which were processed on both Si and Silicon-On-Insulator (SOI) substrates. The high temperature (from 25 °C to 150 °C) influence and different channel lengths and fin widths were also taken into account. While the temperature impact on the intrinsic voltage gain (AV) is limited, the unit gain frequency was strongly affected due to the carrier mobility degradation at higher temperatures, for both p- and n-type FinFET structures. In addition, the pFinFETs showed slightly larger AV values compared to the n-type counterparts, whereby the bulk FinFETs presented a higher dispersion than the SOI FinFETs.LSI/PSI/USP University of Sao Paulo, Av. Prof. Luciano Gualberto, trav. 3 no 158UNESPimec, Kapeldreef 75Dept. of Solid State Sciences Ghent University, Krijgslaan 281 S1EE Depart. KU Leuven, Kasteelpark Arenberg 10UNESPUniversidade de São Paulo (USP)Universidade Estadual Paulista (Unesp)imecGhent UniversityKU LeuvenOliveira, Alberto Vinicius deAgopian, Paula Ghedini Der [UNESP]Martino, Joao AntonioSimoen, EddyClaeys, CorCollaert, NadineThean, Aaron2018-12-11T16:42:27Z2018-12-11T16:42:27Z2016-09-01info:eu-repo/semantics/publishedVersioninfo:eu-repo/semantics/article124-129application/pdfhttp://dx.doi.org/10.1016/j.sse.2016.05.004Solid-State Electronics, v. 123, p. 124-129.0038-1101http://hdl.handle.net/11449/16867110.1016/j.sse.2016.05.0042-s2.0-849695086402-s2.0-84969508640.pdf04969095954656960000-0002-0886-7798Scopusreponame:Repositório Institucional da UNESPinstname:Universidade Estadual Paulista (UNESP)instacron:UNESPengSolid-State Electronics0,492info:eu-repo/semantics/openAccess2023-10-02T06:04:43Zoai:repositorio.unesp.br:11449/168671Repositório InstitucionalPUBhttp://repositorio.unesp.br/oai/requestopendoar:29462023-10-02T06:04:43Repositório Institucional da UNESP - Universidade Estadual Paulista (UNESP)false
dc.title.none.fl_str_mv Comparative analysis of the intrinsic voltage gain and unit gain frequency between SOI and bulk FinFETs up to high temperatures
title Comparative analysis of the intrinsic voltage gain and unit gain frequency between SOI and bulk FinFETs up to high temperatures
spellingShingle Comparative analysis of the intrinsic voltage gain and unit gain frequency between SOI and bulk FinFETs up to high temperatures
Oliveira, Alberto Vinicius de
Analog parameters
Bulk pFinFET
High temperature
SOI pFinFET
title_short Comparative analysis of the intrinsic voltage gain and unit gain frequency between SOI and bulk FinFETs up to high temperatures
title_full Comparative analysis of the intrinsic voltage gain and unit gain frequency between SOI and bulk FinFETs up to high temperatures
title_fullStr Comparative analysis of the intrinsic voltage gain and unit gain frequency between SOI and bulk FinFETs up to high temperatures
title_full_unstemmed Comparative analysis of the intrinsic voltage gain and unit gain frequency between SOI and bulk FinFETs up to high temperatures
title_sort Comparative analysis of the intrinsic voltage gain and unit gain frequency between SOI and bulk FinFETs up to high temperatures
author Oliveira, Alberto Vinicius de
author_facet Oliveira, Alberto Vinicius de
Agopian, Paula Ghedini Der [UNESP]
Martino, Joao Antonio
Simoen, Eddy
Claeys, Cor
Collaert, Nadine
Thean, Aaron
author_role author
author2 Agopian, Paula Ghedini Der [UNESP]
Martino, Joao Antonio
Simoen, Eddy
Claeys, Cor
Collaert, Nadine
Thean, Aaron
author2_role author
author
author
author
author
author
dc.contributor.none.fl_str_mv Universidade de São Paulo (USP)
Universidade Estadual Paulista (Unesp)
imec
Ghent University
KU Leuven
dc.contributor.author.fl_str_mv Oliveira, Alberto Vinicius de
Agopian, Paula Ghedini Der [UNESP]
Martino, Joao Antonio
Simoen, Eddy
Claeys, Cor
Collaert, Nadine
Thean, Aaron
dc.subject.por.fl_str_mv Analog parameters
Bulk pFinFET
High temperature
SOI pFinFET
topic Analog parameters
Bulk pFinFET
High temperature
SOI pFinFET
description This paper presents an experimental analysis of the analog application figures of merit: the intrinsic voltage gain (AV) and unit gain frequency, focusing on the performance comparison between silicon triple gate pFinFET devices, which were processed on both Si and Silicon-On-Insulator (SOI) substrates. The high temperature (from 25 °C to 150 °C) influence and different channel lengths and fin widths were also taken into account. While the temperature impact on the intrinsic voltage gain (AV) is limited, the unit gain frequency was strongly affected due to the carrier mobility degradation at higher temperatures, for both p- and n-type FinFET structures. In addition, the pFinFETs showed slightly larger AV values compared to the n-type counterparts, whereby the bulk FinFETs presented a higher dispersion than the SOI FinFETs.
publishDate 2016
dc.date.none.fl_str_mv 2016-09-01
2018-12-11T16:42:27Z
2018-12-11T16:42:27Z
dc.type.status.fl_str_mv info:eu-repo/semantics/publishedVersion
dc.type.driver.fl_str_mv info:eu-repo/semantics/article
format article
status_str publishedVersion
dc.identifier.uri.fl_str_mv http://dx.doi.org/10.1016/j.sse.2016.05.004
Solid-State Electronics, v. 123, p. 124-129.
0038-1101
http://hdl.handle.net/11449/168671
10.1016/j.sse.2016.05.004
2-s2.0-84969508640
2-s2.0-84969508640.pdf
0496909595465696
0000-0002-0886-7798
url http://dx.doi.org/10.1016/j.sse.2016.05.004
http://hdl.handle.net/11449/168671
identifier_str_mv Solid-State Electronics, v. 123, p. 124-129.
0038-1101
10.1016/j.sse.2016.05.004
2-s2.0-84969508640
2-s2.0-84969508640.pdf
0496909595465696
0000-0002-0886-7798
dc.language.iso.fl_str_mv eng
language eng
dc.relation.none.fl_str_mv Solid-State Electronics
0,492
dc.rights.driver.fl_str_mv info:eu-repo/semantics/openAccess
eu_rights_str_mv openAccess
dc.format.none.fl_str_mv 124-129
application/pdf
dc.source.none.fl_str_mv Scopus
reponame:Repositório Institucional da UNESP
instname:Universidade Estadual Paulista (UNESP)
instacron:UNESP
instname_str Universidade Estadual Paulista (UNESP)
instacron_str UNESP
institution UNESP
reponame_str Repositório Institucional da UNESP
collection Repositório Institucional da UNESP
repository.name.fl_str_mv Repositório Institucional da UNESP - Universidade Estadual Paulista (UNESP)
repository.mail.fl_str_mv
_version_ 1803649290081402880