Back gate influence on transistor efficiency of SOI nMOS Ω-gate nanowire down to 10nm width

• Autor(a) principal: Itocazu, Vitor T.
• Data de Publicação: 2017
• Outros Autores: Almeida, Luciano M., Sonnenberg, Victor, Agopian, Paula G. D. [UNESP], Barraud, Sylvain, Vinet, Maud, Faynot, Olivier, Martino, Joao A.
• Tipo de documento: Artigo de conferência
• Idioma: eng
• Título da fonte: Repositório Institucional da UNESP
• Texto Completo: http://dx.doi.org/10.1109/SBMicro.2017.8113021; http://hdl.handle.net/11449/170552
• topic: Back gate; Nanowire; Omega-Gate; SOI; Transistor Efficiency

This paper shows the influence of back gate bias on transistor efficiency of nMOS SOI Ω-gate nanowire, for different width and channel length. Threshold voltage and subthreshold swing present a higher variation with the back gate bias variation in wider devices. Long channel devices present better efficiency due to the better subthreshold swing, the same reason for the narrow devices have a better efficiency. Wider devices have a higher variation in efficiency when the back gate is biased. The transistor efficiency increases when the back gate is negative biased due to the better electrostatic coupling between gate and channel.