Estudo dos Modos de Configuração de FPGA

• Autor(a) principal: Carbonara, Luigi Pitsch [UNESP]
• Data de Publicação: 2016
• Tipo de documento: Trabalho de conclusão de curso
• Idioma: por
• Título da fonte: Repositório Institucional da UNESP
• Texto Completo: http://hdl.handle.net/11449/155267; http://www.athena.biblioteca.unesp.br/exlibris/bd/capelo/2017-03-31/000881352.pdf
• topic: Circuitos integrados; Configurações; Programadores de computador; Computer programmers

This work shows a study of the FPGA configuration modes from Altera's family CYCLONE IV. The configuration modes allow the FPGA to receive, transmit, process and store data in different ways. The existing configuration modes from the device are Active Serial (AS), Active Parallel (AP), Passive Serial (PS), Fast Passive Parallel (FPP) and Joint Test Action Group (JTAG). In this work, a project pilot was carried out in which is used the JTAG configuration mode targeting to implement a System on Chip (SoC) where we have a processor performing its function in communicating with an additional logic extern to it, being both inserted in the same chip. Also the necessary requirements are presented to a designer perform a FPGA remote configuration from the deepening in the ability of construction of the Nios II processor and its consequent configuration by software with the use of the possible configuration modes which allow this possibility of application, AS and AP