LUTS: A Lightweight User-Level Transaction Scheduler

Detalhes bibliográficos
Autor(a) principal: Nicacio, Daniel
Data de Publicação: 2011
Outros Autores: Baldassin, Alexandro [UNESP], Araujo, Guido, Xiang, Y., Cuzzocrea, A., Hobbs, M., Zhou, W. L.
Tipo de documento: Artigo de conferência
Idioma: eng
Título da fonte: Repositório Institucional da UNESP
Texto Completo: http://hdl.handle.net/11449/194743
Resumo: Software Transactional Memory (STM) systems have poor performance under high contention scenarios. Since many transactions compete for the same data, most of them are aborted, wasting processor runtime. Contention management policies are typically used to avoid that, but they are passive approaches as they wait for an abort to happen so they can take action. More proactive approaches have emerged, trying to predict when a transaction is likely to abort so its execution can be delayed. Such techniques are limited, as they do not replace the doomed transaction by another or, when they do, they rely on the operating system for that, having little or no control on which transaction should run. In this paper we propose LUTS, a Lightweight User-Level Transaction Scheduler, which is based on an execution context record mechanism. Unlike other techniques, LOTS provides the means for selecting another transaction to run in parallel, thus improving system throughput. Moreover, it avoids most of the issues caused by pseudo parallelism, as it only launches as many system-level threads as the number of available processor cores. We discuss LUTS design and present three conflict-avoidance heuristics built around LUTS scheduling capabilities. Experimental results, conducted with STMBench7 and STAMP benchmark suites, show LUTS efficiency when running high contention applications and how conflict-avoidance heuristics can improve STM performance even more. In fact, our transaction scheduling techniques are capable of improving program performance even in overloaded scenarios.
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spelling LUTS: A Lightweight User-Level Transaction SchedulerSoftware Transactional Memory (STM) systems have poor performance under high contention scenarios. Since many transactions compete for the same data, most of them are aborted, wasting processor runtime. Contention management policies are typically used to avoid that, but they are passive approaches as they wait for an abort to happen so they can take action. More proactive approaches have emerged, trying to predict when a transaction is likely to abort so its execution can be delayed. Such techniques are limited, as they do not replace the doomed transaction by another or, when they do, they rely on the operating system for that, having little or no control on which transaction should run. In this paper we propose LUTS, a Lightweight User-Level Transaction Scheduler, which is based on an execution context record mechanism. Unlike other techniques, LOTS provides the means for selecting another transaction to run in parallel, thus improving system throughput. Moreover, it avoids most of the issues caused by pseudo parallelism, as it only launches as many system-level threads as the number of available processor cores. We discuss LUTS design and present three conflict-avoidance heuristics built around LUTS scheduling capabilities. Experimental results, conducted with STMBench7 and STAMP benchmark suites, show LUTS efficiency when running high contention applications and how conflict-avoidance heuristics can improve STM performance even more. In fact, our transaction scheduling techniques are capable of improving program performance even in overloaded scenarios.IC UNICAMP, Campinas, SP, BrazilUniv Estadual Paulista, UNESP, Rio Claro, BrazilUniv Estadual Paulista, UNESP, Rio Claro, BrazilSpringerUniversidade Estadual de Campinas (UNICAMP)Universidade Estadual Paulista (Unesp)Nicacio, DanielBaldassin, Alexandro [UNESP]Araujo, GuidoXiang, Y.Cuzzocrea, A.Hobbs, M.Zhou, W. L.2020-12-10T16:36:17Z2020-12-10T16:36:17Z2011-01-01info:eu-repo/semantics/publishedVersioninfo:eu-repo/semantics/conferenceObject144-+Algorithms And Architectures For Parallel Processing, Pt I. Berlin: Springer-verlag Berlin, v. 7916, p. 144-+, 2011.0302-9743http://hdl.handle.net/11449/194743WOS:000307023100013Web of Sciencereponame:Repositório Institucional da UNESPinstname:Universidade Estadual Paulista (UNESP)instacron:UNESPengAlgorithms And Architectures For Parallel Processing, Pt Iinfo:eu-repo/semantics/openAccess2021-10-22T20:28:44Zoai:repositorio.unesp.br:11449/194743Repositório InstitucionalPUBhttp://repositorio.unesp.br/oai/requestopendoar:29462024-08-05T19:28:43.144634Repositório Institucional da UNESP - Universidade Estadual Paulista (UNESP)false
dc.title.none.fl_str_mv LUTS: A Lightweight User-Level Transaction Scheduler
title LUTS: A Lightweight User-Level Transaction Scheduler
spellingShingle LUTS: A Lightweight User-Level Transaction Scheduler
Nicacio, Daniel
title_short LUTS: A Lightweight User-Level Transaction Scheduler
title_full LUTS: A Lightweight User-Level Transaction Scheduler
title_fullStr LUTS: A Lightweight User-Level Transaction Scheduler
title_full_unstemmed LUTS: A Lightweight User-Level Transaction Scheduler
title_sort LUTS: A Lightweight User-Level Transaction Scheduler
author Nicacio, Daniel
author_facet Nicacio, Daniel
Baldassin, Alexandro [UNESP]
Araujo, Guido
Xiang, Y.
Cuzzocrea, A.
Hobbs, M.
Zhou, W. L.
author_role author
author2 Baldassin, Alexandro [UNESP]
Araujo, Guido
Xiang, Y.
Cuzzocrea, A.
Hobbs, M.
Zhou, W. L.
author2_role author
author
author
author
author
author
dc.contributor.none.fl_str_mv Universidade Estadual de Campinas (UNICAMP)
Universidade Estadual Paulista (Unesp)
dc.contributor.author.fl_str_mv Nicacio, Daniel
Baldassin, Alexandro [UNESP]
Araujo, Guido
Xiang, Y.
Cuzzocrea, A.
Hobbs, M.
Zhou, W. L.
description Software Transactional Memory (STM) systems have poor performance under high contention scenarios. Since many transactions compete for the same data, most of them are aborted, wasting processor runtime. Contention management policies are typically used to avoid that, but they are passive approaches as they wait for an abort to happen so they can take action. More proactive approaches have emerged, trying to predict when a transaction is likely to abort so its execution can be delayed. Such techniques are limited, as they do not replace the doomed transaction by another or, when they do, they rely on the operating system for that, having little or no control on which transaction should run. In this paper we propose LUTS, a Lightweight User-Level Transaction Scheduler, which is based on an execution context record mechanism. Unlike other techniques, LOTS provides the means for selecting another transaction to run in parallel, thus improving system throughput. Moreover, it avoids most of the issues caused by pseudo parallelism, as it only launches as many system-level threads as the number of available processor cores. We discuss LUTS design and present three conflict-avoidance heuristics built around LUTS scheduling capabilities. Experimental results, conducted with STMBench7 and STAMP benchmark suites, show LUTS efficiency when running high contention applications and how conflict-avoidance heuristics can improve STM performance even more. In fact, our transaction scheduling techniques are capable of improving program performance even in overloaded scenarios.
publishDate 2011
dc.date.none.fl_str_mv 2011-01-01
2020-12-10T16:36:17Z
2020-12-10T16:36:17Z
dc.type.status.fl_str_mv info:eu-repo/semantics/publishedVersion
dc.type.driver.fl_str_mv info:eu-repo/semantics/conferenceObject
format conferenceObject
status_str publishedVersion
dc.identifier.uri.fl_str_mv Algorithms And Architectures For Parallel Processing, Pt I. Berlin: Springer-verlag Berlin, v. 7916, p. 144-+, 2011.
0302-9743
http://hdl.handle.net/11449/194743
WOS:000307023100013
identifier_str_mv Algorithms And Architectures For Parallel Processing, Pt I. Berlin: Springer-verlag Berlin, v. 7916, p. 144-+, 2011.
0302-9743
WOS:000307023100013
url http://hdl.handle.net/11449/194743
dc.language.iso.fl_str_mv eng
language eng
dc.relation.none.fl_str_mv Algorithms And Architectures For Parallel Processing, Pt I
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eu_rights_str_mv openAccess
dc.format.none.fl_str_mv 144-+
dc.publisher.none.fl_str_mv Springer
publisher.none.fl_str_mv Springer
dc.source.none.fl_str_mv Web of Science
reponame:Repositório Institucional da UNESP
instname:Universidade Estadual Paulista (UNESP)
instacron:UNESP
instname_str Universidade Estadual Paulista (UNESP)
instacron_str UNESP
institution UNESP
reponame_str Repositório Institucional da UNESP
collection Repositório Institucional da UNESP
repository.name.fl_str_mv Repositório Institucional da UNESP - Universidade Estadual Paulista (UNESP)
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