Estudo teórico e experimental de transistores de múltiplas portas fabricados em estruturas de nanofios

• Autor(a) principal: Perina, Welder Fernandes [UNESP]
• Data de Publicação: 2018
• Tipo de documento: Trabalho de conclusão de curso
• Idioma: por
• Título da fonte: Repositório Institucional da UNESP
• Texto Completo: http://hdl.handle.net/11449/203129; http://www.athena.biblioteca.unesp.br/exlibris/bd/capelo/2019-03-19/000912963.pdf
• topic: Nanofios; Semicondutores de óxido metálico; Tecnologia de silício sobre isolante; Telecomunicações; Transistores; Metal oxide semiconductors; Nanowires; Silicon-on-insulator technology; Telecommunication; Transistors

The technological advancement of semiconductor devices is based on increasing their scalability over the years, ensuring greater performance of electronic circuits and better utilization of the occupied area by integrated circuits. However, with the continuous reduction of the devices, effects such as loss of gate control over the charges in the channel and the influence of drain bias on the threshold voltage, known as short channel effects (SCE), started appearing. The SOI (Silicon-Over-Insulator) technology allowed for a greater reduction of the dimensions of the transistors due to their greater immunity to the SCE. Continuing the technological evolution, 3D transistors have emerged, further enhancing the performance of integrated circuits (the most modern comercially) and enabling the fabrication of even smaller devices. However, it is necessary to study new technologies for the continuation of technological progress, and in this scenario, silicon nanowires appear as one of the alternatives to this evolution. In this work, it was analyzed the digital and analog parameters of Ω-gate nanowires and evaluated digital parameters such as subthershold slope, threshold voltage, maximum transconductance and Drain-Induced Barrier Lowering (DIBL). When evaluating its switching efficiency, represented by subthreshold slope, it was noted that the Ω gate nanowire reaches SS values close to the theoretical limit (60 mV/dec), at room temperature, of the MOSFET technology. By observing the maximum transconductance values, threshold voltage and DIBL, it was possible to analyze indications that the shortest devices were losing the electrostatic control, possibly because of the SCE. The largest and shortest devices presented the worst performance in the case of digital applications, but the narrowest devices showed good results such as high maximum transconductance, low threshold voltage variation with respect to the...