Temperature influence on analog figures-of-merit of nanosheet nMOSFET devices for sub-7nm technology node

Detalhes bibliográficos
Autor(a) principal: Silva, V. C.P.
Data de Publicação: 2020
Outros Autores: Perina, W. F., Martino, J. A. [UNESP], Simoen, E., Veloso, A., Agopian, P. G.D.
Tipo de documento: Artigo de conferência
Idioma: eng
Título da fonte: Repositório Institucional da UNESP
Texto Completo: http://dx.doi.org/10.1109/EUROSOI-ULIS49407.2020.9365565
http://hdl.handle.net/11449/206092
Resumo: This work analyzes the impact of temperature on the Analog figures of Merit of vertically stacked nanosheet nMOSFETs. The excellent electrostatic control between gate and channel results in a strong reduction of the short channel effect, as expected. The analog parameters like the intrinsic voltage gain, transistor efficiency and Early voltage are analyzed as a function of temperature. A high intrinsic voltage gain and a weak temperature dependence are observed, mainly at strong inversion region. The transistor efficiency and subthreshold swing maintain their value close to the theoretical limit.
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spelling Temperature influence on analog figures-of-merit of nanosheet nMOSFET devices for sub-7nm technology nodeAnalog operationMOSFETNanosheets (NS)This work analyzes the impact of temperature on the Analog figures of Merit of vertically stacked nanosheet nMOSFETs. The excellent electrostatic control between gate and channel results in a strong reduction of the short channel effect, as expected. The analog parameters like the intrinsic voltage gain, transistor efficiency and Early voltage are analyzed as a function of temperature. A high intrinsic voltage gain and a weak temperature dependence are observed, mainly at strong inversion region. The transistor efficiency and subthreshold swing maintain their value close to the theoretical limit.LSI/PSI/USP University of Sao PauloImecUNESP Sao Paulo State UniversityUNESP Sao Paulo State UniversityUniversidade de São Paulo (USP)ImecUniversidade Estadual Paulista (Unesp)Silva, V. C.P.Perina, W. F.Martino, J. A. [UNESP]Simoen, E.Veloso, A.Agopian, P. G.D.2021-06-25T10:26:24Z2021-06-25T10:26:24Z2020-09-01info:eu-repo/semantics/publishedVersioninfo:eu-repo/semantics/conferenceObjecthttp://dx.doi.org/10.1109/EUROSOI-ULIS49407.2020.93655652020 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon, EUROSOI-ULIS 2020.http://hdl.handle.net/11449/20609210.1109/EUROSOI-ULIS49407.2020.93655652-s2.0-85102973717Scopusreponame:Repositório Institucional da UNESPinstname:Universidade Estadual Paulista (UNESP)instacron:UNESPeng2020 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon, EUROSOI-ULIS 2020info:eu-repo/semantics/openAccess2021-10-22T20:56:18Zoai:repositorio.unesp.br:11449/206092Repositório InstitucionalPUBhttp://repositorio.unesp.br/oai/requestopendoar:29462021-10-22T20:56:18Repositório Institucional da UNESP - Universidade Estadual Paulista (UNESP)false
dc.title.none.fl_str_mv Temperature influence on analog figures-of-merit of nanosheet nMOSFET devices for sub-7nm technology node
title Temperature influence on analog figures-of-merit of nanosheet nMOSFET devices for sub-7nm technology node
spellingShingle Temperature influence on analog figures-of-merit of nanosheet nMOSFET devices for sub-7nm technology node
Silva, V. C.P.
Analog operation
MOSFET
Nanosheets (NS)
title_short Temperature influence on analog figures-of-merit of nanosheet nMOSFET devices for sub-7nm technology node
title_full Temperature influence on analog figures-of-merit of nanosheet nMOSFET devices for sub-7nm technology node
title_fullStr Temperature influence on analog figures-of-merit of nanosheet nMOSFET devices for sub-7nm technology node
title_full_unstemmed Temperature influence on analog figures-of-merit of nanosheet nMOSFET devices for sub-7nm technology node
title_sort Temperature influence on analog figures-of-merit of nanosheet nMOSFET devices for sub-7nm technology node
author Silva, V. C.P.
author_facet Silva, V. C.P.
Perina, W. F.
Martino, J. A. [UNESP]
Simoen, E.
Veloso, A.
Agopian, P. G.D.
author_role author
author2 Perina, W. F.
Martino, J. A. [UNESP]
Simoen, E.
Veloso, A.
Agopian, P. G.D.
author2_role author
author
author
author
author
dc.contributor.none.fl_str_mv Universidade de São Paulo (USP)
Imec
Universidade Estadual Paulista (Unesp)
dc.contributor.author.fl_str_mv Silva, V. C.P.
Perina, W. F.
Martino, J. A. [UNESP]
Simoen, E.
Veloso, A.
Agopian, P. G.D.
dc.subject.por.fl_str_mv Analog operation
MOSFET
Nanosheets (NS)
topic Analog operation
MOSFET
Nanosheets (NS)
description This work analyzes the impact of temperature on the Analog figures of Merit of vertically stacked nanosheet nMOSFETs. The excellent electrostatic control between gate and channel results in a strong reduction of the short channel effect, as expected. The analog parameters like the intrinsic voltage gain, transistor efficiency and Early voltage are analyzed as a function of temperature. A high intrinsic voltage gain and a weak temperature dependence are observed, mainly at strong inversion region. The transistor efficiency and subthreshold swing maintain their value close to the theoretical limit.
publishDate 2020
dc.date.none.fl_str_mv 2020-09-01
2021-06-25T10:26:24Z
2021-06-25T10:26:24Z
dc.type.status.fl_str_mv info:eu-repo/semantics/publishedVersion
dc.type.driver.fl_str_mv info:eu-repo/semantics/conferenceObject
format conferenceObject
status_str publishedVersion
dc.identifier.uri.fl_str_mv http://dx.doi.org/10.1109/EUROSOI-ULIS49407.2020.9365565
2020 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon, EUROSOI-ULIS 2020.
http://hdl.handle.net/11449/206092
10.1109/EUROSOI-ULIS49407.2020.9365565
2-s2.0-85102973717
url http://dx.doi.org/10.1109/EUROSOI-ULIS49407.2020.9365565
http://hdl.handle.net/11449/206092
identifier_str_mv 2020 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon, EUROSOI-ULIS 2020.
10.1109/EUROSOI-ULIS49407.2020.9365565
2-s2.0-85102973717
dc.language.iso.fl_str_mv eng
language eng
dc.relation.none.fl_str_mv 2020 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon, EUROSOI-ULIS 2020
dc.rights.driver.fl_str_mv info:eu-repo/semantics/openAccess
eu_rights_str_mv openAccess
dc.source.none.fl_str_mv Scopus
reponame:Repositório Institucional da UNESP
instname:Universidade Estadual Paulista (UNESP)
instacron:UNESP
instname_str Universidade Estadual Paulista (UNESP)
instacron_str UNESP
institution UNESP
reponame_str Repositório Institucional da UNESP
collection Repositório Institucional da UNESP
repository.name.fl_str_mv Repositório Institucional da UNESP - Universidade Estadual Paulista (UNESP)
repository.mail.fl_str_mv
_version_ 1799965558816374784

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