Operational Transconductance Amplifier Design with Gate- All-Around Nanosheet MOSFET using Experimental Lookup Table Approach
Autor(a) principal: | |
---|---|
Data de Publicação: | 2021 |
Outros Autores: | , , , , , |
Tipo de documento: | Artigo de conferência |
Idioma: | eng |
Título da fonte: | Repositório Institucional da UNESP |
Texto Completo: | http://dx.doi.org/10.1109/EuroSOI-ULIS53016.2021.9560689 http://hdl.handle.net/11449/237554 |
Resumo: | This paper presents the design of an Operational Transconductance Amplifier (OTA) with Gate-All-Around Nanosheet MOSFETs (GAA-NSH). The circuit simulation was performed using an experimental Lookup Table (LUT) approach. The experimental drain current and gate capacitance were extracted and used in a Verilog-A model in order to design the OTA for different transistor efficiency (gm/ID) values. The results present a compromise between power consumption (PC), voltage gain (Av) and the Gain-Bandwidth-Product (GBW). For gm/In of 8 V-1 an Av of 71.8 dB is obtained for a GBW of 361.3 MHz. These results were compared with other OTA designs using FinFET and TFET devices. The NSH OTA presents higher GBW, and considering the Av and PC, while NSH present better behavior than FinFETs, the behavior is worse than TFET OTA circuit for strong inversion operation. |
id |
UNSP_aca8ee82e8c573a3af25ae89ee33de43 |
---|---|
oai_identifier_str |
oai:repositorio.unesp.br:11449/237554 |
network_acronym_str |
UNSP |
network_name_str |
Repositório Institucional da UNESP |
repository_id_str |
2946 |
spelling |
Operational Transconductance Amplifier Design with Gate- All-Around Nanosheet MOSFET using Experimental Lookup Table ApproachNanosheet (NSH)Operational Transconductance AmplifierTransistor Efficiency (g(m)/I-D)Lookup TableAnalog Circuit DesignThis paper presents the design of an Operational Transconductance Amplifier (OTA) with Gate-All-Around Nanosheet MOSFETs (GAA-NSH). The circuit simulation was performed using an experimental Lookup Table (LUT) approach. The experimental drain current and gate capacitance were extracted and used in a Verilog-A model in order to design the OTA for different transistor efficiency (gm/ID) values. The results present a compromise between power consumption (PC), voltage gain (Av) and the Gain-Bandwidth-Product (GBW). For gm/In of 8 V-1 an Av of 71.8 dB is obtained for a GBW of 361.3 MHz. These results were compared with other OTA designs using FinFET and TFET devices. The NSH OTA presents higher GBW, and considering the Av and PC, while NSH present better behavior than FinFETs, the behavior is worse than TFET OTA circuit for strong inversion operation.Conselho Nacional de Desenvolvimento Científico e Tecnológico (CNPq)Coordenação de Aperfeiçoamento de Pessoal de Nível Superior (CAPES)Univ Sao Paulo, LSI PSI USP, Sao Paulo, BrazilIMEC, Leuven, BelgiumSao Paulo State Univ, UNESP, Sao Joao Da Boa Vista, BrazilSao Paulo State Univ, UNESP, Sao Joao Da Boa Vista, BrazilIeeeUniversidade de São Paulo (USP)IMECUniversidade Estadual Paulista (UNESP)Sousa, Julia C. S.Perina, Welder F.Simoen, EddyVeloso, AnabelaMartino, Joao A.Agopian, Paula G. D. [UNESP]IEEE2022-11-30T13:38:23Z2022-11-30T13:38:23Z2021-01-01info:eu-repo/semantics/publishedVersioninfo:eu-repo/semantics/conferenceObject4http://dx.doi.org/10.1109/EuroSOI-ULIS53016.2021.95606892021 Joint International Eurosoi Workshop And International Conference On Ultimate Integration On Silicon (eurosoi-ulis). New York: Ieee, 4 p., 2021.2330-5738http://hdl.handle.net/11449/23755410.1109/EuroSOI-ULIS53016.2021.9560689WOS:000790181800039Web of Sciencereponame:Repositório Institucional da UNESPinstname:Universidade Estadual Paulista (UNESP)instacron:UNESPeng2021 Joint International Eurosoi Workshop And International Conference On Ultimate Integration On Silicon (eurosoi-ulis)info:eu-repo/semantics/openAccess2022-11-30T13:38:23Zoai:repositorio.unesp.br:11449/237554Repositório InstitucionalPUBhttp://repositorio.unesp.br/oai/requestopendoar:29462024-08-05T14:27:02.588058Repositório Institucional da UNESP - Universidade Estadual Paulista (UNESP)false |
dc.title.none.fl_str_mv |
Operational Transconductance Amplifier Design with Gate- All-Around Nanosheet MOSFET using Experimental Lookup Table Approach |
title |
Operational Transconductance Amplifier Design with Gate- All-Around Nanosheet MOSFET using Experimental Lookup Table Approach |
spellingShingle |
Operational Transconductance Amplifier Design with Gate- All-Around Nanosheet MOSFET using Experimental Lookup Table Approach Sousa, Julia C. S. Nanosheet (NSH) Operational Transconductance Amplifier Transistor Efficiency (g(m)/I-D) Lookup Table Analog Circuit Design |
title_short |
Operational Transconductance Amplifier Design with Gate- All-Around Nanosheet MOSFET using Experimental Lookup Table Approach |
title_full |
Operational Transconductance Amplifier Design with Gate- All-Around Nanosheet MOSFET using Experimental Lookup Table Approach |
title_fullStr |
Operational Transconductance Amplifier Design with Gate- All-Around Nanosheet MOSFET using Experimental Lookup Table Approach |
title_full_unstemmed |
Operational Transconductance Amplifier Design with Gate- All-Around Nanosheet MOSFET using Experimental Lookup Table Approach |
title_sort |
Operational Transconductance Amplifier Design with Gate- All-Around Nanosheet MOSFET using Experimental Lookup Table Approach |
author |
Sousa, Julia C. S. |
author_facet |
Sousa, Julia C. S. Perina, Welder F. Simoen, Eddy Veloso, Anabela Martino, Joao A. Agopian, Paula G. D. [UNESP] IEEE |
author_role |
author |
author2 |
Perina, Welder F. Simoen, Eddy Veloso, Anabela Martino, Joao A. Agopian, Paula G. D. [UNESP] IEEE |
author2_role |
author author author author author author |
dc.contributor.none.fl_str_mv |
Universidade de São Paulo (USP) IMEC Universidade Estadual Paulista (UNESP) |
dc.contributor.author.fl_str_mv |
Sousa, Julia C. S. Perina, Welder F. Simoen, Eddy Veloso, Anabela Martino, Joao A. Agopian, Paula G. D. [UNESP] IEEE |
dc.subject.por.fl_str_mv |
Nanosheet (NSH) Operational Transconductance Amplifier Transistor Efficiency (g(m)/I-D) Lookup Table Analog Circuit Design |
topic |
Nanosheet (NSH) Operational Transconductance Amplifier Transistor Efficiency (g(m)/I-D) Lookup Table Analog Circuit Design |
description |
This paper presents the design of an Operational Transconductance Amplifier (OTA) with Gate-All-Around Nanosheet MOSFETs (GAA-NSH). The circuit simulation was performed using an experimental Lookup Table (LUT) approach. The experimental drain current and gate capacitance were extracted and used in a Verilog-A model in order to design the OTA for different transistor efficiency (gm/ID) values. The results present a compromise between power consumption (PC), voltage gain (Av) and the Gain-Bandwidth-Product (GBW). For gm/In of 8 V-1 an Av of 71.8 dB is obtained for a GBW of 361.3 MHz. These results were compared with other OTA designs using FinFET and TFET devices. The NSH OTA presents higher GBW, and considering the Av and PC, while NSH present better behavior than FinFETs, the behavior is worse than TFET OTA circuit for strong inversion operation. |
publishDate |
2021 |
dc.date.none.fl_str_mv |
2021-01-01 2022-11-30T13:38:23Z 2022-11-30T13:38:23Z |
dc.type.status.fl_str_mv |
info:eu-repo/semantics/publishedVersion |
dc.type.driver.fl_str_mv |
info:eu-repo/semantics/conferenceObject |
format |
conferenceObject |
status_str |
publishedVersion |
dc.identifier.uri.fl_str_mv |
http://dx.doi.org/10.1109/EuroSOI-ULIS53016.2021.9560689 2021 Joint International Eurosoi Workshop And International Conference On Ultimate Integration On Silicon (eurosoi-ulis). New York: Ieee, 4 p., 2021. 2330-5738 http://hdl.handle.net/11449/237554 10.1109/EuroSOI-ULIS53016.2021.9560689 WOS:000790181800039 |
url |
http://dx.doi.org/10.1109/EuroSOI-ULIS53016.2021.9560689 http://hdl.handle.net/11449/237554 |
identifier_str_mv |
2021 Joint International Eurosoi Workshop And International Conference On Ultimate Integration On Silicon (eurosoi-ulis). New York: Ieee, 4 p., 2021. 2330-5738 10.1109/EuroSOI-ULIS53016.2021.9560689 WOS:000790181800039 |
dc.language.iso.fl_str_mv |
eng |
language |
eng |
dc.relation.none.fl_str_mv |
2021 Joint International Eurosoi Workshop And International Conference On Ultimate Integration On Silicon (eurosoi-ulis) |
dc.rights.driver.fl_str_mv |
info:eu-repo/semantics/openAccess |
eu_rights_str_mv |
openAccess |
dc.format.none.fl_str_mv |
4 |
dc.publisher.none.fl_str_mv |
Ieee |
publisher.none.fl_str_mv |
Ieee |
dc.source.none.fl_str_mv |
Web of Science reponame:Repositório Institucional da UNESP instname:Universidade Estadual Paulista (UNESP) instacron:UNESP |
instname_str |
Universidade Estadual Paulista (UNESP) |
instacron_str |
UNESP |
institution |
UNESP |
reponame_str |
Repositório Institucional da UNESP |
collection |
Repositório Institucional da UNESP |
repository.name.fl_str_mv |
Repositório Institucional da UNESP - Universidade Estadual Paulista (UNESP) |
repository.mail.fl_str_mv |
|
_version_ |
1808128361630793728 |