Low power SAR analog-to-digital converter for internet-of-things RF receivers
Autor(a) principal: | |
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Data de Publicação: | 2018 |
Tipo de documento: | Dissertação |
Idioma: | eng |
Título da fonte: | Biblioteca Digital de Teses e Dissertações da UFRGS |
Texto Completo: | http://hdl.handle.net/10183/186015 |
Resumo: | The "Internet of Things" (IoT) has been a topic of intensive research in industry, technological centers and academic community, being data communication one aspect of high relevance in this area. The exponential increase of devices with wireless capabilities as well as the number of users, alongside with the decreasing costs for implementation of broadband communications, created a suitable environment for IoT applications. An IoT device is typically composed by a wireless transceiver, a battery and/or energy harvesting unit, a power management unit, sensors and conditioning unit, a microprocessor and data storage unit. Energy supply is a limiting factor in many applications and the transceiver usually demands a significant amount of power. In this scenario the emerging wireless communication standard IEEE 802.11ah, in which this work focuses, was proposed as an option for low power sub-GHz radio communication. A typical architecture of modern radio receivers contains the analog radio-frequency (RF) front-end, which amplifies, demodulates and filters the input signal, and also analog-to-digital converters (ADC), that translate the analog signals to the digital domain. Additionally, the Successive-Approximation (SAR) ADC architecture has become popular recently due to its power efficiency, simplicity, and compatibility with scaled-down integrated CMOS technology. In this work, the RF receiver architecture and its specifications aiming low power consumption and IEEE 802.11ah standard complying are outlined, being the basis to the proposition of an 8-bit resolution and 10 MHz sampling rate ADC. A power efficient switching scheme for the charge redistribution SAR ADC architecture is explored in detail, along with the circuit-level design of the digital-to-analog converter (DAC). The transistor-level design of the two remaining ADC main blocks, sampling switch and comparator, are also explored. Electrical simulation of the physical layout, including parasitics, at a 130nm CMOS process resulted in a SINAD of 47:3 dB and 45:5 dB and at the receiver IF 3 MHz and at the Nyquist rate, respectively, consuming 21 W with a power supply of 1 V . The SAR ADC resulting Figure-of-Merit (FoM) corresponded to 11:1 fJ/conv-step at IF, and 13:7 fJ/conv-step at the Nyquist rate. |
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Dornelas, Helga UchoaKlimach, Hamilton DuarteFabris, Eric Ericson2018-12-06T02:45:35Z2018http://hdl.handle.net/10183/186015001082279The "Internet of Things" (IoT) has been a topic of intensive research in industry, technological centers and academic community, being data communication one aspect of high relevance in this area. The exponential increase of devices with wireless capabilities as well as the number of users, alongside with the decreasing costs for implementation of broadband communications, created a suitable environment for IoT applications. An IoT device is typically composed by a wireless transceiver, a battery and/or energy harvesting unit, a power management unit, sensors and conditioning unit, a microprocessor and data storage unit. Energy supply is a limiting factor in many applications and the transceiver usually demands a significant amount of power. In this scenario the emerging wireless communication standard IEEE 802.11ah, in which this work focuses, was proposed as an option for low power sub-GHz radio communication. A typical architecture of modern radio receivers contains the analog radio-frequency (RF) front-end, which amplifies, demodulates and filters the input signal, and also analog-to-digital converters (ADC), that translate the analog signals to the digital domain. Additionally, the Successive-Approximation (SAR) ADC architecture has become popular recently due to its power efficiency, simplicity, and compatibility with scaled-down integrated CMOS technology. In this work, the RF receiver architecture and its specifications aiming low power consumption and IEEE 802.11ah standard complying are outlined, being the basis to the proposition of an 8-bit resolution and 10 MHz sampling rate ADC. A power efficient switching scheme for the charge redistribution SAR ADC architecture is explored in detail, along with the circuit-level design of the digital-to-analog converter (DAC). The transistor-level design of the two remaining ADC main blocks, sampling switch and comparator, are also explored. Electrical simulation of the physical layout, including parasitics, at a 130nm CMOS process resulted in a SINAD of 47:3 dB and 45:5 dB and at the receiver IF 3 MHz and at the Nyquist rate, respectively, consuming 21 W with a power supply of 1 V . The SAR ADC resulting Figure-of-Merit (FoM) corresponded to 11:1 fJ/conv-step at IF, and 13:7 fJ/conv-step at the Nyquist rate.application/pdfengMicroeletrônicaCmosInternet das coisasCMOS Analog DesignInternet of ThingsSuccessive Approximation ADCLow Power DesignAnalog to Digital ConverterLow power SAR analog-to-digital converter for internet-of-things RF receiversConversor analógico-digital SAR de baixo consumo para receptores RF de internet-das-coisas info:eu-repo/semantics/publishedVersioninfo:eu-repo/semantics/masterThesisUniversidade Federal do Rio Grande do SulInstituto de InformáticaPrograma de Pós-Graduação em MicroeletrônicaPorto Alegre, BR-RS2018mestradoinfo:eu-repo/semantics/openAccessreponame:Biblioteca Digital de Teses e Dissertações da UFRGSinstname:Universidade Federal do Rio Grande do Sul (UFRGS)instacron:UFRGSTEXT001082279.pdf.txt001082279.pdf.txtExtracted Texttext/plain200218http://www.lume.ufrgs.br/bitstream/10183/186015/2/001082279.pdf.txtb971e656c13638518e7126b02038abbfMD52ORIGINAL001082279.pdfTexto completo (inglês)application/pdf7290286http://www.lume.ufrgs.br/bitstream/10183/186015/1/001082279.pdf29ed73df7a35c5a86b0cf8a3ff782877MD5110183/1860152021-05-26 04:43:54.441073oai:www.lume.ufrgs.br:10183/186015Biblioteca Digital de Teses e Dissertaçõeshttps://lume.ufrgs.br/handle/10183/2PUBhttps://lume.ufrgs.br/oai/requestlume@ufrgs.br||lume@ufrgs.bropendoar:18532021-05-26T07:43:54Biblioteca Digital de Teses e Dissertações da UFRGS - Universidade Federal do Rio Grande do Sul (UFRGS)false |
dc.title.pt_BR.fl_str_mv |
Low power SAR analog-to-digital converter for internet-of-things RF receivers |
dc.title.alternative.pt.fl_str_mv |
Conversor analógico-digital SAR de baixo consumo para receptores RF de internet-das-coisas |
title |
Low power SAR analog-to-digital converter for internet-of-things RF receivers |
spellingShingle |
Low power SAR analog-to-digital converter for internet-of-things RF receivers Dornelas, Helga Uchoa Microeletrônica Cmos Internet das coisas CMOS Analog Design Internet of Things Successive Approximation ADC Low Power Design Analog to Digital Converter |
title_short |
Low power SAR analog-to-digital converter for internet-of-things RF receivers |
title_full |
Low power SAR analog-to-digital converter for internet-of-things RF receivers |
title_fullStr |
Low power SAR analog-to-digital converter for internet-of-things RF receivers |
title_full_unstemmed |
Low power SAR analog-to-digital converter for internet-of-things RF receivers |
title_sort |
Low power SAR analog-to-digital converter for internet-of-things RF receivers |
author |
Dornelas, Helga Uchoa |
author_facet |
Dornelas, Helga Uchoa |
author_role |
author |
dc.contributor.author.fl_str_mv |
Dornelas, Helga Uchoa |
dc.contributor.advisor1.fl_str_mv |
Klimach, Hamilton Duarte |
dc.contributor.advisor-co1.fl_str_mv |
Fabris, Eric Ericson |
contributor_str_mv |
Klimach, Hamilton Duarte Fabris, Eric Ericson |
dc.subject.por.fl_str_mv |
Microeletrônica Cmos Internet das coisas |
topic |
Microeletrônica Cmos Internet das coisas CMOS Analog Design Internet of Things Successive Approximation ADC Low Power Design Analog to Digital Converter |
dc.subject.eng.fl_str_mv |
CMOS Analog Design Internet of Things Successive Approximation ADC Low Power Design Analog to Digital Converter |
description |
The "Internet of Things" (IoT) has been a topic of intensive research in industry, technological centers and academic community, being data communication one aspect of high relevance in this area. The exponential increase of devices with wireless capabilities as well as the number of users, alongside with the decreasing costs for implementation of broadband communications, created a suitable environment for IoT applications. An IoT device is typically composed by a wireless transceiver, a battery and/or energy harvesting unit, a power management unit, sensors and conditioning unit, a microprocessor and data storage unit. Energy supply is a limiting factor in many applications and the transceiver usually demands a significant amount of power. In this scenario the emerging wireless communication standard IEEE 802.11ah, in which this work focuses, was proposed as an option for low power sub-GHz radio communication. A typical architecture of modern radio receivers contains the analog radio-frequency (RF) front-end, which amplifies, demodulates and filters the input signal, and also analog-to-digital converters (ADC), that translate the analog signals to the digital domain. Additionally, the Successive-Approximation (SAR) ADC architecture has become popular recently due to its power efficiency, simplicity, and compatibility with scaled-down integrated CMOS technology. In this work, the RF receiver architecture and its specifications aiming low power consumption and IEEE 802.11ah standard complying are outlined, being the basis to the proposition of an 8-bit resolution and 10 MHz sampling rate ADC. A power efficient switching scheme for the charge redistribution SAR ADC architecture is explored in detail, along with the circuit-level design of the digital-to-analog converter (DAC). The transistor-level design of the two remaining ADC main blocks, sampling switch and comparator, are also explored. Electrical simulation of the physical layout, including parasitics, at a 130nm CMOS process resulted in a SINAD of 47:3 dB and 45:5 dB and at the receiver IF 3 MHz and at the Nyquist rate, respectively, consuming 21 W with a power supply of 1 V . The SAR ADC resulting Figure-of-Merit (FoM) corresponded to 11:1 fJ/conv-step at IF, and 13:7 fJ/conv-step at the Nyquist rate. |
publishDate |
2018 |
dc.date.accessioned.fl_str_mv |
2018-12-06T02:45:35Z |
dc.date.issued.fl_str_mv |
2018 |
dc.type.status.fl_str_mv |
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info:eu-repo/semantics/masterThesis |
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