Boundary scan test, test methodology, and fault modeling

• Autor(a) principal: Frans de Jong
• Data de Publicação: 1991
• Outros Autores: José S. Matos, José M. Ferreira
• Tipo de documento: Artigo
• Idioma: eng
• Título da fonte: Repositório Científico de Acesso Aberto de Portugal (Repositórios Cientìficos)
• Texto Completo: https://hdl.handle.net/10216/84545
• topic: Engenharia electrotécnica, Engenharia electrotécnica, electrónica e informática; Electrical engineering, Electrical engineering, Electronic engineering, Information engineering

The test technique called "boundary scan test" (BST) offers new opportunities in testing but confronts users with new problems too. The implementation of BST in a chip has become an IEEE standard and users on board level are the next group to begin thinking about using the new possibilities. This article addresses some of the questions about changes in board-level testing and fault diagnosis. The fault model itself is also affected by using BST. Trivial items are extended with more sophisticated details in order to complete the fault model. Finally, BST appears to be a test technique that offers a high degree of detectability on board level, but for diagnosis, some additional effort has to be made.