Fast convolutional neural networks in low density FPGAs using zero-skipping and weight pruning
Autor(a) principal: | |
---|---|
Data de Publicação: | 2019 |
Outros Autores: | , , |
Tipo de documento: | Artigo |
Idioma: | eng |
Título da fonte: | Repositório Científico de Acesso Aberto de Portugal (Repositórios Cientìficos) |
Texto Completo: | http://hdl.handle.net/10400.21/10735 |
Resumo: | Edge devices are becoming smarter with the integration of machine learning methods, such as deep learning, and are therefore used in many application domains where decisions have to be made without human intervention. Deep learning and, in particular, convolutional neural networks (CNN) are more efficient than previous algorithms for several computer vision applications such as security and surveillance, where image and video analysis are required. This better efficiency comes with a cost of high computation and memory requirements. Hence, running CNNs in embedded computing devices is a challenge for both algorithm and hardware designers. New processing devices, dedicated system architectures and optimization of the networks have been researched to deal with these computation requirements. In this paper, we improve the inference execution times of CNNs in low density FPGAs (Field-Programmable Gate Arrays) using fixed-point arithmetic, zero-skipping and weight pruning. The developed architecture supports the execution of large CNNs in FPGA devices with reduced on-chip memory and computing resources. With the proposed architecture, it is possible to infer an image in AlexNet in 2.9 ms in a ZYNQ7020 and 1.0 ms in a ZYNQ7045 with less than 1% accuracy degradation. These results improve previous state-of-the-art architectures for CNN inference. |
id |
RCAP_412607c31530d381a97105f0710eb021 |
---|---|
oai_identifier_str |
oai:repositorio.ipl.pt:10400.21/10735 |
network_acronym_str |
RCAP |
network_name_str |
Repositório Científico de Acesso Aberto de Portugal (Repositórios Cientìficos) |
repository_id_str |
7160 |
spelling |
Fast convolutional neural networks in low density FPGAs using zero-skipping and weight pruningDeep learningConvolutional neural networkSmart edge devicesZero-skippingPruningFPGAEdge devices are becoming smarter with the integration of machine learning methods, such as deep learning, and are therefore used in many application domains where decisions have to be made without human intervention. Deep learning and, in particular, convolutional neural networks (CNN) are more efficient than previous algorithms for several computer vision applications such as security and surveillance, where image and video analysis are required. This better efficiency comes with a cost of high computation and memory requirements. Hence, running CNNs in embedded computing devices is a challenge for both algorithm and hardware designers. New processing devices, dedicated system architectures and optimization of the networks have been researched to deal with these computation requirements. In this paper, we improve the inference execution times of CNNs in low density FPGAs (Field-Programmable Gate Arrays) using fixed-point arithmetic, zero-skipping and weight pruning. The developed architecture supports the execution of large CNNs in FPGA devices with reduced on-chip memory and computing resources. With the proposed architecture, it is possible to infer an image in AlexNet in 2.9 ms in a ZYNQ7020 and 1.0 ms in a ZYNQ7045 with less than 1% accuracy degradation. These results improve previous state-of-the-art architectures for CNN inference.MDPIRCIPLVéstias, MárioDuarte, Rui PolicarpoDe Sousa, JoseCláudio de Campos Neto, Horácio2019-11-25T11:15:23Z2019-11-092019-11-09T00:00:00Zinfo:eu-repo/semantics/publishedVersioninfo:eu-repo/semantics/articleapplication/pdfhttp://hdl.handle.net/10400.21/10735engVÉSTIAS, Mário P.; [et al] – Fast convolutional neural networks in low density FPGAs using zero-skipping and weight pruning. Electronics. ISSN 2079-9292. Vol. 8, N.º 11 (2019), pp. 1-242079-929210.3390/electronics8111321info:eu-repo/semantics/openAccessreponame:Repositório Científico de Acesso Aberto de Portugal (Repositórios Cientìficos)instname:Agência para a Sociedade do Conhecimento (UMIC) - FCT - Sociedade da Informaçãoinstacron:RCAAP2023-08-03T10:01:07Zoai:repositorio.ipl.pt:10400.21/10735Portal AgregadorONGhttps://www.rcaap.pt/oai/openaireopendoar:71602024-03-19T20:19:05.647785Repositório Científico de Acesso Aberto de Portugal (Repositórios Cientìficos) - Agência para a Sociedade do Conhecimento (UMIC) - FCT - Sociedade da Informaçãofalse |
dc.title.none.fl_str_mv |
Fast convolutional neural networks in low density FPGAs using zero-skipping and weight pruning |
title |
Fast convolutional neural networks in low density FPGAs using zero-skipping and weight pruning |
spellingShingle |
Fast convolutional neural networks in low density FPGAs using zero-skipping and weight pruning Véstias, Mário Deep learning Convolutional neural network Smart edge devices Zero-skipping Pruning FPGA |
title_short |
Fast convolutional neural networks in low density FPGAs using zero-skipping and weight pruning |
title_full |
Fast convolutional neural networks in low density FPGAs using zero-skipping and weight pruning |
title_fullStr |
Fast convolutional neural networks in low density FPGAs using zero-skipping and weight pruning |
title_full_unstemmed |
Fast convolutional neural networks in low density FPGAs using zero-skipping and weight pruning |
title_sort |
Fast convolutional neural networks in low density FPGAs using zero-skipping and weight pruning |
author |
Véstias, Mário |
author_facet |
Véstias, Mário Duarte, Rui Policarpo De Sousa, Jose Cláudio de Campos Neto, Horácio |
author_role |
author |
author2 |
Duarte, Rui Policarpo De Sousa, Jose Cláudio de Campos Neto, Horácio |
author2_role |
author author author |
dc.contributor.none.fl_str_mv |
RCIPL |
dc.contributor.author.fl_str_mv |
Véstias, Mário Duarte, Rui Policarpo De Sousa, Jose Cláudio de Campos Neto, Horácio |
dc.subject.por.fl_str_mv |
Deep learning Convolutional neural network Smart edge devices Zero-skipping Pruning FPGA |
topic |
Deep learning Convolutional neural network Smart edge devices Zero-skipping Pruning FPGA |
description |
Edge devices are becoming smarter with the integration of machine learning methods, such as deep learning, and are therefore used in many application domains where decisions have to be made without human intervention. Deep learning and, in particular, convolutional neural networks (CNN) are more efficient than previous algorithms for several computer vision applications such as security and surveillance, where image and video analysis are required. This better efficiency comes with a cost of high computation and memory requirements. Hence, running CNNs in embedded computing devices is a challenge for both algorithm and hardware designers. New processing devices, dedicated system architectures and optimization of the networks have been researched to deal with these computation requirements. In this paper, we improve the inference execution times of CNNs in low density FPGAs (Field-Programmable Gate Arrays) using fixed-point arithmetic, zero-skipping and weight pruning. The developed architecture supports the execution of large CNNs in FPGA devices with reduced on-chip memory and computing resources. With the proposed architecture, it is possible to infer an image in AlexNet in 2.9 ms in a ZYNQ7020 and 1.0 ms in a ZYNQ7045 with less than 1% accuracy degradation. These results improve previous state-of-the-art architectures for CNN inference. |
publishDate |
2019 |
dc.date.none.fl_str_mv |
2019-11-25T11:15:23Z 2019-11-09 2019-11-09T00:00:00Z |
dc.type.status.fl_str_mv |
info:eu-repo/semantics/publishedVersion |
dc.type.driver.fl_str_mv |
info:eu-repo/semantics/article |
format |
article |
status_str |
publishedVersion |
dc.identifier.uri.fl_str_mv |
http://hdl.handle.net/10400.21/10735 |
url |
http://hdl.handle.net/10400.21/10735 |
dc.language.iso.fl_str_mv |
eng |
language |
eng |
dc.relation.none.fl_str_mv |
VÉSTIAS, Mário P.; [et al] – Fast convolutional neural networks in low density FPGAs using zero-skipping and weight pruning. Electronics. ISSN 2079-9292. Vol. 8, N.º 11 (2019), pp. 1-24 2079-9292 10.3390/electronics8111321 |
dc.rights.driver.fl_str_mv |
info:eu-repo/semantics/openAccess |
eu_rights_str_mv |
openAccess |
dc.format.none.fl_str_mv |
application/pdf |
dc.publisher.none.fl_str_mv |
MDPI |
publisher.none.fl_str_mv |
MDPI |
dc.source.none.fl_str_mv |
reponame:Repositório Científico de Acesso Aberto de Portugal (Repositórios Cientìficos) instname:Agência para a Sociedade do Conhecimento (UMIC) - FCT - Sociedade da Informação instacron:RCAAP |
instname_str |
Agência para a Sociedade do Conhecimento (UMIC) - FCT - Sociedade da Informação |
instacron_str |
RCAAP |
institution |
RCAAP |
reponame_str |
Repositório Científico de Acesso Aberto de Portugal (Repositórios Cientìficos) |
collection |
Repositório Científico de Acesso Aberto de Portugal (Repositórios Cientìficos) |
repository.name.fl_str_mv |
Repositório Científico de Acesso Aberto de Portugal (Repositórios Cientìficos) - Agência para a Sociedade do Conhecimento (UMIC) - FCT - Sociedade da Informação |
repository.mail.fl_str_mv |
|
_version_ |
1799133456702111744 |