A fast and scalable architecture to run convolutional neural networks in low density FPGAs

Véstias, Mário; Duarte, Rui; De Sousa, Jose; Neto, Horácio C

A fast and scalable architecture to run convolutional neural networks in low density FPGAs

Detalhes bibliográficos
Autor(a) principal:	Véstias, Mário
Data de Publicação:	2020
Outros Autores:	Duarte, Rui, De Sousa, Jose, Neto, Horácio C
Tipo de documento:	Artigo
Idioma:	eng
Título da fonte:	Repositório Científico de Acesso Aberto de Portugal (Repositórios Cientìficos)
Texto Completo:	http://hdl.handle.net/10400.21/12279
Resumo:	Este trabalho foi financiado pelo Concurso Anual para Projetos de Investigação, Desenvolvimento, Inovação e Criação Artística (IDI&CA) 2016 do Instituto Politécnico de Lisboa. Código de referência IPL/2019/inCNeuraINet_ISEL

Metadados do item

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network_name_str	Repositório Científico de Acesso Aberto de Portugal (Repositórios Cientìficos)
repository_id_str	7160
spelling	A fast and scalable architecture to run convolutional neural networks in low density FPGAsDeep learningConvolutional neural networkSmart edge devicesFPGAEste trabalho foi financiado pelo Concurso Anual para Projetos de Investigação, Desenvolvimento, Inovação e Criação Artística (IDI&CA) 2016 do Instituto Politécnico de Lisboa. Código de referência IPL/2019/inCNeuraINet_ISELDeep learning and, in particular, convolutional neural networks (CNN) achieve very good results on several computer vision applications like security and surveillance, where image and video analysis are required. These networks are quite demanding in terms of computation and memory and therefore are usually implemented in high-performance computing platforms or devices. Running CNNs in embedded platforms or devices with low computational and memory resources requires a careful optimization of system architectures and algorithms to obtain very efficient designs. In this context, Field Programmable Gate Arrays (FPGA) can achieve this efficiency since the programmable hardware fabric can be tailored for each specific network. In this paper, a very efficient configurable architecture for CNN inference targeting any density FPGAs is described. The architecture considers fixed-point arithmetic and image batch to reduce computational, memory and memory bandwidth requirements without compromising network accuracy. The developed architecture supports the execution of large CNNs in any FPGA devices including those with small on-chip memory size and logic resources. With the proposed architecture, it is possible to infer an image in AlexNet in 4.3 ms in a ZYNQ7020 and 1.2 ms in a ZYNQ7045.ElsevierRCIPLVéstias, MárioDuarte, RuiDe Sousa, JoseNeto, Horácio C2020-10-07T14:07:34Z2020-092020-09-01T00:00:00Zinfo:eu-repo/semantics/publishedVersioninfo:eu-repo/semantics/articleapplication/pdfhttp://hdl.handle.net/10400.21/12279engVÉSTIAS, Mário P.; [et al] – A fast and scalable architecture to run convolutional neural networks in low density FPGAs. Microprocessors and Microsystems. ISSN 0141-9331. Vol. 77 (2020), pp. 1-150141-933110.1016/j.micpro.2020.103136metadata only accessinfo:eu-repo/semantics/openAccessreponame:Repositório Científico de Acesso Aberto de Portugal (Repositórios Cientìficos)instname:Agência para a Sociedade do Conhecimento (UMIC) - FCT - Sociedade da Informaçãoinstacron:RCAAP2023-08-03T10:04:53Zoai:repositorio.ipl.pt:10400.21/12279Portal AgregadorONGhttps://www.rcaap.pt/oai/openaireopendoar:71602024-03-19T20:20:24.013490Repositório Científico de Acesso Aberto de Portugal (Repositórios Cientìficos) - Agência para a Sociedade do Conhecimento (UMIC) - FCT - Sociedade da Informaçãofalse
dc.title.none.fl_str_mv	A fast and scalable architecture to run convolutional neural networks in low density FPGAs
title	A fast and scalable architecture to run convolutional neural networks in low density FPGAs
spellingShingle	A fast and scalable architecture to run convolutional neural networks in low density FPGAs Véstias, Mário Deep learning Convolutional neural network Smart edge devices FPGA
title_short	A fast and scalable architecture to run convolutional neural networks in low density FPGAs
title_full	A fast and scalable architecture to run convolutional neural networks in low density FPGAs
title_fullStr	A fast and scalable architecture to run convolutional neural networks in low density FPGAs
title_full_unstemmed	A fast and scalable architecture to run convolutional neural networks in low density FPGAs
title_sort	A fast and scalable architecture to run convolutional neural networks in low density FPGAs
author	Véstias, Mário
author_facet	Véstias, Mário Duarte, Rui De Sousa, Jose Neto, Horácio C
author_role	author
author2	Duarte, Rui De Sousa, Jose Neto, Horácio C
author2_role	author author author
dc.contributor.none.fl_str_mv	RCIPL
dc.contributor.author.fl_str_mv	Véstias, Mário Duarte, Rui De Sousa, Jose Neto, Horácio C
dc.subject.por.fl_str_mv	Deep learning Convolutional neural network Smart edge devices FPGA
topic	Deep learning Convolutional neural network Smart edge devices FPGA
description	Este trabalho foi financiado pelo Concurso Anual para Projetos de Investigação, Desenvolvimento, Inovação e Criação Artística (IDI&CA) 2016 do Instituto Politécnico de Lisboa. Código de referência IPL/2019/inCNeuraINet_ISEL
publishDate	2020
dc.date.none.fl_str_mv	2020-10-07T14:07:34Z 2020-09 2020-09-01T00:00:00Z
dc.type.status.fl_str_mv	info:eu-repo/semantics/publishedVersion
dc.type.driver.fl_str_mv	info:eu-repo/semantics/article
format	article
status_str	publishedVersion
dc.identifier.uri.fl_str_mv	http://hdl.handle.net/10400.21/12279
url	http://hdl.handle.net/10400.21/12279
dc.language.iso.fl_str_mv	eng
language	eng
dc.relation.none.fl_str_mv	VÉSTIAS, Mário P.; [et al] – A fast and scalable architecture to run convolutional neural networks in low density FPGAs. Microprocessors and Microsystems. ISSN 0141-9331. Vol. 77 (2020), pp. 1-15 0141-9331 10.1016/j.micpro.2020.103136
dc.rights.driver.fl_str_mv	metadata only access info:eu-repo/semantics/openAccess
rights_invalid_str_mv	metadata only access
eu_rights_str_mv	openAccess
dc.format.none.fl_str_mv	application/pdf
dc.publisher.none.fl_str_mv	Elsevier
publisher.none.fl_str_mv	Elsevier
dc.source.none.fl_str_mv	reponame:Repositório Científico de Acesso Aberto de Portugal (Repositórios Cientìficos) instname:Agência para a Sociedade do Conhecimento (UMIC) - FCT - Sociedade da Informação instacron:RCAAP
instname_str	Agência para a Sociedade do Conhecimento (UMIC) - FCT - Sociedade da Informação
instacron_str	RCAAP
institution	RCAAP
reponame_str	Repositório Científico de Acesso Aberto de Portugal (Repositórios Cientìficos)
collection	Repositório Científico de Acesso Aberto de Portugal (Repositórios Cientìficos)
repository.name.fl_str_mv	Repositório Científico de Acesso Aberto de Portugal (Repositórios Cientìficos) - Agência para a Sociedade do Conhecimento (UMIC) - FCT - Sociedade da Informação
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A fast and scalable architecture to run convolutional neural networks in low density FPGAs

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