An 18GHz Wide-Band Buffer

• Autor(a) principal: Sebastião, Daniel Neto
• Data de Publicação: 2022
• Tipo de documento: Dissertação
• Idioma: eng
• Título da fonte: Repositório Científico de Acesso Aberto de Portugal (Repositórios Cientìficos)
• Texto Completo: http://hdl.handle.net/10362/155743
• topic: 6G; ADC; Direct-conversion; Input Buffer; 7 nm FinFET; Wide-Band; Domínio/Área Científica::Engenharia e Tecnologia::Engenharia Eletrotécnica, Eletrónica e Informática

Recent developments in wireless communication and systems, such as sixth-generation (6G), radar and instrumentation have led to massive use of high-frequency carriers. As a result, there is a high demand for Analog-to-Digital Converters (ADCs) in direct-conversion architectures with high bandwidth, high-resolution, and with the highest possible power efficiency and spectral purity. A potential performance enhancement of an ADC can be realized by adding a voltage Input Buffer (IB). To increase the IB bandwidth and decrease the distortion from the nonlinear sampling circuit, a low output impedance is required. Therefore, to achieve low output impedance, it is necessary to dissipate power that is often equal to or greater than the power dissipated in the rest of the ADC blocks combined, since the output impedance is inversely proportional to the bias current. Consequently, input buffers are one of the most "power-hungry" building blocks of any direct receiver chain. In recent years, due to the high ADC resolution and quantization range, the existing approaches use IBs with supply voltages above the nominal rails, for instance, 2.5 or 4.0 V, to increase the linearity and to not limit the ADC output swing. However, it inherently creates reliability and robustness issues. This work investigates several different input buffers implemented in 7 nm FinFET technology with 1.8V of supply voltage in which a one pico farad of sampling capacitance is driven. The study starts by exploring four single-stage topologies in thick gate devices with and without linearity techniques, for example, the drain-source voltage "bootstrap" technique. Moreover, two bandwidth extension techniques are introduced, for instance, the Bridge T-coil with Series Peaking and the Distributed Approach. Lastly, two-stage IB architectures with thick oxide devices together with thin oxide devices are implemented. Finally, the new solutions presented meet the requirements by exhibiting more than 18 GHz of bandwidth with a linearity (IIP3) higher than 16.3 dBm, and a DC power consumption lower than 178.2 mW without compromising reliability and robustness issues.