Design of High-Bandwidth and High-Linearity Input Buffers for ADCs
Autor(a) principal: | |
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Data de Publicação: | 2020 |
Tipo de documento: | Dissertação |
Idioma: | eng |
Título da fonte: | Repositório Científico de Acesso Aberto de Portugal (Repositórios Cientìficos) |
Texto Completo: | http://hdl.handle.net/10362/110350 |
Resumo: | Nowadays on-chip Input Buffers (IBs) for direct conversion front-ends are realized with a higher voltage supply than that of the core voltage of the technology, mainly for linearity purposes. This, in turn, makes it mandatory to have more than one voltage source to supply a single chip in addition to having devices capable of handling higher voltages. This work explores the possibility of having IBs supplied with the technology’s core voltage to standardize all of the devices and reducing the different voltage supply sources and/or voltage regulators needed for operating the front-end drivers of the Analog to Digital Converters (ADCs). A new input buffer architecture will be presented and compared to some prior input buffer implementations in the same conditions. This new architecture presents good linearity and bandwidth results and can be used for input buffers with the added benefit of not needing higher voltages nor special devices. This new architecture is based off an existing one with another feedback loop to improved high-frequency peaking and linearity issues. This architecture achieves better results in bandwidth, a SNDR of 58 dB with and output voltage of 600 mV peak-to-peak differential. Furthermore, this buffer achieves a better efficiency linearity-wise when comparing to other buffers in the same conditions. |
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Design of High-Bandwidth and High-Linearity Input Buffers for ADCsADCInput BufferCMOSHigh LinearityHigh BandwidthDirect ConversionDomínio/Área Científica::Engenharia e Tecnologia::Engenharia Eletrotécnica, Eletrónica e InformáticaNowadays on-chip Input Buffers (IBs) for direct conversion front-ends are realized with a higher voltage supply than that of the core voltage of the technology, mainly for linearity purposes. This, in turn, makes it mandatory to have more than one voltage source to supply a single chip in addition to having devices capable of handling higher voltages. This work explores the possibility of having IBs supplied with the technology’s core voltage to standardize all of the devices and reducing the different voltage supply sources and/or voltage regulators needed for operating the front-end drivers of the Analog to Digital Converters (ADCs). A new input buffer architecture will be presented and compared to some prior input buffer implementations in the same conditions. This new architecture presents good linearity and bandwidth results and can be used for input buffers with the added benefit of not needing higher voltages nor special devices. This new architecture is based off an existing one with another feedback loop to improved high-frequency peaking and linearity issues. This architecture achieves better results in bandwidth, a SNDR of 58 dB with and output voltage of 600 mV peak-to-peak differential. Furthermore, this buffer achieves a better efficiency linearity-wise when comparing to other buffers in the same conditions.Goes, JoãoRUNLeonardo, David Barros2021-01-18T12:15:19Z2020-1220202020-12-01T00:00:00Zinfo:eu-repo/semantics/publishedVersioninfo:eu-repo/semantics/masterThesisapplication/pdfhttp://hdl.handle.net/10362/110350enginfo:eu-repo/semantics/openAccessreponame:Repositório Científico de Acesso Aberto de Portugal (Repositórios Cientìficos)instname:Agência para a Sociedade do Conhecimento (UMIC) - FCT - Sociedade da Informaçãoinstacron:RCAAP2024-03-11T04:54:03Zoai:run.unl.pt:10362/110350Portal AgregadorONGhttps://www.rcaap.pt/oai/openaireopendoar:71602024-03-20T03:41:32.741148Repositório Científico de Acesso Aberto de Portugal (Repositórios Cientìficos) - Agência para a Sociedade do Conhecimento (UMIC) - FCT - Sociedade da Informaçãofalse |
dc.title.none.fl_str_mv |
Design of High-Bandwidth and High-Linearity Input Buffers for ADCs |
title |
Design of High-Bandwidth and High-Linearity Input Buffers for ADCs |
spellingShingle |
Design of High-Bandwidth and High-Linearity Input Buffers for ADCs Leonardo, David Barros ADC Input Buffer CMOS High Linearity High Bandwidth Direct Conversion Domínio/Área Científica::Engenharia e Tecnologia::Engenharia Eletrotécnica, Eletrónica e Informática |
title_short |
Design of High-Bandwidth and High-Linearity Input Buffers for ADCs |
title_full |
Design of High-Bandwidth and High-Linearity Input Buffers for ADCs |
title_fullStr |
Design of High-Bandwidth and High-Linearity Input Buffers for ADCs |
title_full_unstemmed |
Design of High-Bandwidth and High-Linearity Input Buffers for ADCs |
title_sort |
Design of High-Bandwidth and High-Linearity Input Buffers for ADCs |
author |
Leonardo, David Barros |
author_facet |
Leonardo, David Barros |
author_role |
author |
dc.contributor.none.fl_str_mv |
Goes, João RUN |
dc.contributor.author.fl_str_mv |
Leonardo, David Barros |
dc.subject.por.fl_str_mv |
ADC Input Buffer CMOS High Linearity High Bandwidth Direct Conversion Domínio/Área Científica::Engenharia e Tecnologia::Engenharia Eletrotécnica, Eletrónica e Informática |
topic |
ADC Input Buffer CMOS High Linearity High Bandwidth Direct Conversion Domínio/Área Científica::Engenharia e Tecnologia::Engenharia Eletrotécnica, Eletrónica e Informática |
description |
Nowadays on-chip Input Buffers (IBs) for direct conversion front-ends are realized with a higher voltage supply than that of the core voltage of the technology, mainly for linearity purposes. This, in turn, makes it mandatory to have more than one voltage source to supply a single chip in addition to having devices capable of handling higher voltages. This work explores the possibility of having IBs supplied with the technology’s core voltage to standardize all of the devices and reducing the different voltage supply sources and/or voltage regulators needed for operating the front-end drivers of the Analog to Digital Converters (ADCs). A new input buffer architecture will be presented and compared to some prior input buffer implementations in the same conditions. This new architecture presents good linearity and bandwidth results and can be used for input buffers with the added benefit of not needing higher voltages nor special devices. This new architecture is based off an existing one with another feedback loop to improved high-frequency peaking and linearity issues. This architecture achieves better results in bandwidth, a SNDR of 58 dB with and output voltage of 600 mV peak-to-peak differential. Furthermore, this buffer achieves a better efficiency linearity-wise when comparing to other buffers in the same conditions. |
publishDate |
2020 |
dc.date.none.fl_str_mv |
2020-12 2020 2020-12-01T00:00:00Z 2021-01-18T12:15:19Z |
dc.type.status.fl_str_mv |
info:eu-repo/semantics/publishedVersion |
dc.type.driver.fl_str_mv |
info:eu-repo/semantics/masterThesis |
format |
masterThesis |
status_str |
publishedVersion |
dc.identifier.uri.fl_str_mv |
http://hdl.handle.net/10362/110350 |
url |
http://hdl.handle.net/10362/110350 |
dc.language.iso.fl_str_mv |
eng |
language |
eng |
dc.rights.driver.fl_str_mv |
info:eu-repo/semantics/openAccess |
eu_rights_str_mv |
openAccess |
dc.format.none.fl_str_mv |
application/pdf |
dc.source.none.fl_str_mv |
reponame:Repositório Científico de Acesso Aberto de Portugal (Repositórios Cientìficos) instname:Agência para a Sociedade do Conhecimento (UMIC) - FCT - Sociedade da Informação instacron:RCAAP |
instname_str |
Agência para a Sociedade do Conhecimento (UMIC) - FCT - Sociedade da Informação |
instacron_str |
RCAAP |
institution |
RCAAP |
reponame_str |
Repositório Científico de Acesso Aberto de Portugal (Repositórios Cientìficos) |
collection |
Repositório Científico de Acesso Aberto de Portugal (Repositórios Cientìficos) |
repository.name.fl_str_mv |
Repositório Científico de Acesso Aberto de Portugal (Repositórios Cientìficos) - Agência para a Sociedade do Conhecimento (UMIC) - FCT - Sociedade da Informação |
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1799138028867813376 |