Wafer-level packaging fo RF applications : using high resistivity polycrystalline silicon substrate technology

Detalhes bibliográficos
Autor(a) principal: Polyakov, A.
Data de Publicação: 2004
Outros Autores: Sinaga, S. M., Mendes, P. M., Bartek, M., Correia, J. H., Burghartz, J. N.
Idioma: eng
Título da fonte: Repositório Científico de Acesso Aberto de Portugal (Repositórios Cientìficos)
Texto Completo: http://hdl.handle.net/1822/4880
Resumo: High-resistivity polycrystalline silicon (HRPS) wafers are explored as a novel low-cost and low-loss substrate in Wafer-Level Chip-Size Packaging (WLCSP) for RF applications. The WLCSP solution we demonstrate is based on adhesive bonding of a HRPS wafer to a silicon wafer with active devices. After bonding, the IC wafer is thinned below 50 µm and selectively removed to expose its front-side contact pads. The HRPS wafer serves as a mechanical carrier, thermal spreader and vertical spacer in which vias are etched by DRIE to reach desired pads on the IC wafer. Then after a seed layer sputtering, a 5-10 µm Cu layer is plated on both wafer sides and patterned providing a back-side ground plane and large, front-side RF passives. Due to HRPS electrical properties, no dielectric isolation layer is required inside vias, simplifying the front-side processing. Solder bumping on the substrate backside and singulation by dicing complete the processing. The presented concept enables integration of large RF passives with a spacing of >150 µm to the conductive silicon substrate containing the circuitry, while providing mechanical stability, reducing form factor and avoiding any additional RF loss. Antenna performance comparable to glass substrates and high quality factors for large spiral inductors (Q=11 at 1 GHz; 34 nH) are demonstrated. The HRPS substrates have high dielectric constant, low RF loss, high thermal conductivity, perfect thermal matching, and processing similar to the single-crystalline silicon.
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spelling Wafer-level packaging fo RF applications : using high resistivity polycrystalline silicon substrate technologyPolycrystalline siliconWafer-level packagingHigh-resistivy silicion substrateIntegrated passivesDielectric lossesSubstrate transferRF applicationsHigh-resistivity polycrystalline silicon (HRPS) wafers are explored as a novel low-cost and low-loss substrate in Wafer-Level Chip-Size Packaging (WLCSP) for RF applications. The WLCSP solution we demonstrate is based on adhesive bonding of a HRPS wafer to a silicon wafer with active devices. After bonding, the IC wafer is thinned below 50 µm and selectively removed to expose its front-side contact pads. The HRPS wafer serves as a mechanical carrier, thermal spreader and vertical spacer in which vias are etched by DRIE to reach desired pads on the IC wafer. Then after a seed layer sputtering, a 5-10 µm Cu layer is plated on both wafer sides and patterned providing a back-side ground plane and large, front-side RF passives. Due to HRPS electrical properties, no dielectric isolation layer is required inside vias, simplifying the front-side processing. Solder bumping on the substrate backside and singulation by dicing complete the processing. The presented concept enables integration of large RF passives with a spacing of >150 µm to the conductive silicon substrate containing the circuitry, while providing mechanical stability, reducing form factor and avoiding any additional RF loss. Antenna performance comparable to glass substrates and high quality factors for large spiral inductors (Q=11 at 1 GHz; 34 nH) are demonstrated. The HRPS substrates have high dielectric constant, low RF loss, high thermal conductivity, perfect thermal matching, and processing similar to the single-crystalline silicon.Fundação para a Ciência e a Tecnologia (FCT) – SFRH/BD/4717/2001, POCTI/ESSE/38469/2001, FEDER.Comunidade Europeia (CE) – (project Blue Whale IST – 2000 – 3006).IMAPSUniversidade do MinhoPolyakov, A.Sinaga, S. M.Mendes, P. M.Bartek, M.Correia, J. H.Burghartz, J. N.2004-11-142004-11-14T00:00:00Zconference paperinfo:eu-repo/semantics/publishedVersionapplication/pdfhttp://hdl.handle.net/1822/4880engINTERNATIONAL MICROELECTRONICS AND PACKAGING SOCIETY (IMAPS), 2004, California, USA– “International Microelectronics and Packaging Society : proceedings”. [Long Beach] : IMAPS, 2004. ISBN 0-930815-74-2.0-930815-74-2info:eu-repo/semantics/openAccessreponame:Repositório Científico de Acesso Aberto de Portugal (Repositórios Cientìficos)instname:Agência para a Sociedade do Conhecimento (UMIC) - FCT - Sociedade da Informaçãoinstacron:RCAAP2024-05-11T06:47:49Zoai:repositorium.sdum.uminho.pt:1822/4880Portal AgregadorONGhttps://www.rcaap.pt/oai/openairemluisa.alvim@gmail.comopendoar:71602024-05-11T06:47:49Repositório Científico de Acesso Aberto de Portugal (Repositórios Cientìficos) - Agência para a Sociedade do Conhecimento (UMIC) - FCT - Sociedade da Informaçãofalse
dc.title.none.fl_str_mv Wafer-level packaging fo RF applications : using high resistivity polycrystalline silicon substrate technology
title Wafer-level packaging fo RF applications : using high resistivity polycrystalline silicon substrate technology
spellingShingle Wafer-level packaging fo RF applications : using high resistivity polycrystalline silicon substrate technology
Polyakov, A.
Polycrystalline silicon
Wafer-level packaging
High-resistivy silicion substrate
Integrated passives
Dielectric losses
Substrate transfer
RF applications
title_short Wafer-level packaging fo RF applications : using high resistivity polycrystalline silicon substrate technology
title_full Wafer-level packaging fo RF applications : using high resistivity polycrystalline silicon substrate technology
title_fullStr Wafer-level packaging fo RF applications : using high resistivity polycrystalline silicon substrate technology
title_full_unstemmed Wafer-level packaging fo RF applications : using high resistivity polycrystalline silicon substrate technology
title_sort Wafer-level packaging fo RF applications : using high resistivity polycrystalline silicon substrate technology
author Polyakov, A.
author_facet Polyakov, A.
Sinaga, S. M.
Mendes, P. M.
Bartek, M.
Correia, J. H.
Burghartz, J. N.
author_role author
author2 Sinaga, S. M.
Mendes, P. M.
Bartek, M.
Correia, J. H.
Burghartz, J. N.
author2_role author
author
author
author
author
dc.contributor.none.fl_str_mv Universidade do Minho
dc.contributor.author.fl_str_mv Polyakov, A.
Sinaga, S. M.
Mendes, P. M.
Bartek, M.
Correia, J. H.
Burghartz, J. N.
dc.subject.por.fl_str_mv Polycrystalline silicon
Wafer-level packaging
High-resistivy silicion substrate
Integrated passives
Dielectric losses
Substrate transfer
RF applications
topic Polycrystalline silicon
Wafer-level packaging
High-resistivy silicion substrate
Integrated passives
Dielectric losses
Substrate transfer
RF applications
description High-resistivity polycrystalline silicon (HRPS) wafers are explored as a novel low-cost and low-loss substrate in Wafer-Level Chip-Size Packaging (WLCSP) for RF applications. The WLCSP solution we demonstrate is based on adhesive bonding of a HRPS wafer to a silicon wafer with active devices. After bonding, the IC wafer is thinned below 50 µm and selectively removed to expose its front-side contact pads. The HRPS wafer serves as a mechanical carrier, thermal spreader and vertical spacer in which vias are etched by DRIE to reach desired pads on the IC wafer. Then after a seed layer sputtering, a 5-10 µm Cu layer is plated on both wafer sides and patterned providing a back-side ground plane and large, front-side RF passives. Due to HRPS electrical properties, no dielectric isolation layer is required inside vias, simplifying the front-side processing. Solder bumping on the substrate backside and singulation by dicing complete the processing. The presented concept enables integration of large RF passives with a spacing of >150 µm to the conductive silicon substrate containing the circuitry, while providing mechanical stability, reducing form factor and avoiding any additional RF loss. Antenna performance comparable to glass substrates and high quality factors for large spiral inductors (Q=11 at 1 GHz; 34 nH) are demonstrated. The HRPS substrates have high dielectric constant, low RF loss, high thermal conductivity, perfect thermal matching, and processing similar to the single-crystalline silicon.
publishDate 2004
dc.date.none.fl_str_mv 2004-11-14
2004-11-14T00:00:00Z
dc.type.driver.fl_str_mv conference paper
dc.type.status.fl_str_mv info:eu-repo/semantics/publishedVersion
status_str publishedVersion
dc.identifier.uri.fl_str_mv http://hdl.handle.net/1822/4880
url http://hdl.handle.net/1822/4880
dc.language.iso.fl_str_mv eng
language eng
dc.relation.none.fl_str_mv INTERNATIONAL MICROELECTRONICS AND PACKAGING SOCIETY (IMAPS), 2004, California, USA– “International Microelectronics and Packaging Society : proceedings”. [Long Beach] : IMAPS, 2004. ISBN 0-930815-74-2.
0-930815-74-2
dc.rights.driver.fl_str_mv info:eu-repo/semantics/openAccess
eu_rights_str_mv openAccess
dc.format.none.fl_str_mv application/pdf
dc.publisher.none.fl_str_mv IMAPS
publisher.none.fl_str_mv IMAPS
dc.source.none.fl_str_mv reponame:Repositório Científico de Acesso Aberto de Portugal (Repositórios Cientìficos)
instname:Agência para a Sociedade do Conhecimento (UMIC) - FCT - Sociedade da Informação
instacron:RCAAP
instname_str Agência para a Sociedade do Conhecimento (UMIC) - FCT - Sociedade da Informação
instacron_str RCAAP
institution RCAAP
reponame_str Repositório Científico de Acesso Aberto de Portugal (Repositórios Cientìficos)
collection Repositório Científico de Acesso Aberto de Portugal (Repositórios Cientìficos)
repository.name.fl_str_mv Repositório Científico de Acesso Aberto de Portugal (Repositórios Cientìficos) - Agência para a Sociedade do Conhecimento (UMIC) - FCT - Sociedade da Informação
repository.mail.fl_str_mv mluisa.alvim@gmail.com
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