Solving differential equations in analog domain

Detalhes bibliográficos
Autor(a) principal: Silva, Duarte Gonçalves Lopes da
Data de Publicação: 2023
Tipo de documento: Dissertação
Idioma: eng
Título da fonte: Repositório Científico de Acesso Aberto de Portugal (Repositórios Cientìficos)
Texto Completo: http://hdl.handle.net/10362/162021
Resumo: A growth in the use of analog computers has been seen in the last few years despite of the dominance of digital computers, this is due to the fact that it was noticed that analog computers could solve differential equations not only faster but also in a more efficient way, which means drawing less power. This lead to the interest in studying how a computer can solve this type of equations and what it takes to do so. With this in mind a circuit that describes a variation of the law of exponential decay is proposed, this implicated the design of an folded cascode operational amplifier, which was implemented using 130nm MOS technology. This then led to the study of this amplifier in an integrator configuration as well as the proposed circuit, which in a later stage was made configurable by adding a logic controller to control the resistors that establish the coefficients of the equation. With the obtained results it was possible to validate the objective specifications for the amplifier as well as observe that the circuit was able to come to successful results within the known constraints of the components used for this circuit. This circuit was able to reach solutions much faster than a digital computer facing the same problem, 30s versus 0.3s, while consuming considerably less power, 40mW versus 72W.
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spelling Solving differential equations in analog domainAnalog computingDifferential equation solverCMOSFolded-CascodeIntegratorDomínio/Área Científica::Engenharia e Tecnologia::Engenharia Eletrotécnica, Eletrónica e InformáticaA growth in the use of analog computers has been seen in the last few years despite of the dominance of digital computers, this is due to the fact that it was noticed that analog computers could solve differential equations not only faster but also in a more efficient way, which means drawing less power. This lead to the interest in studying how a computer can solve this type of equations and what it takes to do so. With this in mind a circuit that describes a variation of the law of exponential decay is proposed, this implicated the design of an folded cascode operational amplifier, which was implemented using 130nm MOS technology. This then led to the study of this amplifier in an integrator configuration as well as the proposed circuit, which in a later stage was made configurable by adding a logic controller to control the resistors that establish the coefficients of the equation. With the obtained results it was possible to validate the objective specifications for the amplifier as well as observe that the circuit was able to come to successful results within the known constraints of the components used for this circuit. This circuit was able to reach solutions much faster than a digital computer facing the same problem, 30s versus 0.3s, while consuming considerably less power, 40mW versus 72W.Nos últimos anos tem se verificado um aumento no uso de computadores analógicos apesar do contínuo domínio por parte dos computadores digitais, isto deve-se principalmente ao facto de que foi observado que os computadores analógicos conseguem não só resolver equações diferenciais muito mais rápidos, mas também que estes conseguem fazê-lo de uma maneira muito mais eficiente, ou seja, gastando menos potência. Isto levou ao interesse em estudar como estes computadores resolvem estas equações e também o que é necessário para o fazer. Devido as estes fatores, um circuito que representa uma variante da lei de decaimento exponencial foi proposto para ser resolvido, isto implicou o dimensionamento de um amplificador operacional de topologia "folded-cascode", que foi implementado usando tecnologia MOS de 130nm. Isto levou ao estudo deste amplificador na sua montagem integradora para além do circuito proposto, por fim este circuito foi tornado configurável por meio de um controlador lógico adicional a controlar as resistências que determinam os valores dos coeficientes desta equação. Com os resultados obtidos, foi não só possível validar que as características definidas para o amplificador foram cumpridas como também observar que o circuito conseguiu obter resultados bem sucedidos dentro das limitações dos componentes do circuito. Assim este circuito conseguiu chegar ao resultado destas equações num tempo muito inferior ao de um computador digital, 30s contra 0.3s, enquanto consumia uma potência estimada consideravelmente mais baixa, 40mW contra 72W.Oliveira, LuísRUNSilva, Duarte Gonçalves Lopes da2024-01-08T16:18:08Z2023-112023-11-01T00:00:00Zinfo:eu-repo/semantics/publishedVersioninfo:eu-repo/semantics/masterThesisapplication/pdfhttp://hdl.handle.net/10362/162021enginfo:eu-repo/semantics/openAccessreponame:Repositório Científico de Acesso Aberto de Portugal (Repositórios Cientìficos)instname:Agência para a Sociedade do Conhecimento (UMIC) - FCT - Sociedade da Informaçãoinstacron:RCAAP2024-03-11T05:43:51Zoai:run.unl.pt:10362/162021Portal AgregadorONGhttps://www.rcaap.pt/oai/openaireopendoar:71602024-03-20T03:58:19.687307Repositório Científico de Acesso Aberto de Portugal (Repositórios Cientìficos) - Agência para a Sociedade do Conhecimento (UMIC) - FCT - Sociedade da Informaçãofalse
dc.title.none.fl_str_mv Solving differential equations in analog domain
title Solving differential equations in analog domain
spellingShingle Solving differential equations in analog domain
Silva, Duarte Gonçalves Lopes da
Analog computing
Differential equation solver
CMOS
Folded-Cascode
Integrator
Domínio/Área Científica::Engenharia e Tecnologia::Engenharia Eletrotécnica, Eletrónica e Informática
title_short Solving differential equations in analog domain
title_full Solving differential equations in analog domain
title_fullStr Solving differential equations in analog domain
title_full_unstemmed Solving differential equations in analog domain
title_sort Solving differential equations in analog domain
author Silva, Duarte Gonçalves Lopes da
author_facet Silva, Duarte Gonçalves Lopes da
author_role author
dc.contributor.none.fl_str_mv Oliveira, Luís
RUN
dc.contributor.author.fl_str_mv Silva, Duarte Gonçalves Lopes da
dc.subject.por.fl_str_mv Analog computing
Differential equation solver
CMOS
Folded-Cascode
Integrator
Domínio/Área Científica::Engenharia e Tecnologia::Engenharia Eletrotécnica, Eletrónica e Informática
topic Analog computing
Differential equation solver
CMOS
Folded-Cascode
Integrator
Domínio/Área Científica::Engenharia e Tecnologia::Engenharia Eletrotécnica, Eletrónica e Informática
description A growth in the use of analog computers has been seen in the last few years despite of the dominance of digital computers, this is due to the fact that it was noticed that analog computers could solve differential equations not only faster but also in a more efficient way, which means drawing less power. This lead to the interest in studying how a computer can solve this type of equations and what it takes to do so. With this in mind a circuit that describes a variation of the law of exponential decay is proposed, this implicated the design of an folded cascode operational amplifier, which was implemented using 130nm MOS technology. This then led to the study of this amplifier in an integrator configuration as well as the proposed circuit, which in a later stage was made configurable by adding a logic controller to control the resistors that establish the coefficients of the equation. With the obtained results it was possible to validate the objective specifications for the amplifier as well as observe that the circuit was able to come to successful results within the known constraints of the components used for this circuit. This circuit was able to reach solutions much faster than a digital computer facing the same problem, 30s versus 0.3s, while consuming considerably less power, 40mW versus 72W.
publishDate 2023
dc.date.none.fl_str_mv 2023-11
2023-11-01T00:00:00Z
2024-01-08T16:18:08Z
dc.type.status.fl_str_mv info:eu-repo/semantics/publishedVersion
dc.type.driver.fl_str_mv info:eu-repo/semantics/masterThesis
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dc.identifier.uri.fl_str_mv http://hdl.handle.net/10362/162021
url http://hdl.handle.net/10362/162021
dc.language.iso.fl_str_mv eng
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