Design of a Moderate-Resolution Dual-Slope ADC using Noise-Shaping Techniques and a Double Speed Quantizer

• Autor(a) principal: Fernandes, João Daniel Caneira
• Data de Publicação: 2018
• Tipo de documento: Dissertação
• Idioma: eng
• Título da fonte: Repositório Científico de Acesso Aberto de Portugal (Repositórios Cientìficos)
• Texto Completo: http://hdl.handle.net/10362/61684
• topic: Analog-to-Digital Converter; Integrating Quantizer; Dual-Slope Quantizer; Dual-Slope Quantizer; 2-Bit Quantizer; Double-Speed Quantizer; Domínio/Área Científica::Engenharia e Tecnologia::Engenharia Eletrotécnica, Eletrónica e Informática

Being the slowest Analog-to-Digital Converter, the Dual-Slope quantizer is often used in sigma-delta ADC or SAR converter architectures, and in measurement instruments, due to its high accuracy. Despite the utility of the quantizer and the existent techniques to increase the accuracy and the conversion speed, the usability of this converter is still very limited by the its slow conversion rate. The main interest of the Dual-Slope Quantizer lies in the high accuracy from the quantization technique used. To convert the input value, the value is integrated in the charge phase, by an integrator circuit, to be quantized, in the discharging phase using a digital block. Other benefits of the Dual-Slope Quantizers are the small size when implemented in a system on a chip (SOC) and the low power consumption. By reducing the the conversion time of this ADC, while maintaining the high accuracy it will be possible to increase the converters utility, such as in IoT devices, or even mobile devices, benefiting all from the high accuracy and low power consumption of this circuit. Nowadays, many techniques are being used in the Dual-Slope converters, such as, the addition of bi-directional capabilities, to increase the conversion speed, the addition of an half LSB compensation, to increase the accuracy, and the use of Noise-Shaping capabilities originated from the quantization error from each discharge phase. All of this techniques are presented and used in this research. For the proposed solution, a Double-Speed Quantizer composed of two additional comparators will be added to grant the conversion speed increase, which will increase the power consumption and will lead to a redesigning of the digital block to receive more inputs. As result the conversion speed will double in comparison to the existent 4 bit dual slope quantizer, being needed 8 clock cycles to quantize a input value, instead of 16.