Dynamically rotate and free for test: the aath for FPGA concurrent test

• Autor(a) principal: Manuel Gericota
• Data de Publicação: 2001
• Outros Autores: Gustavo Costa Alves, José Martins Ferreira
• Tipo de documento: Livro
• Idioma: eng
• Título da fonte: Repositório Científico de Acesso Aberto de Portugal (Repositórios Cientìficos)
• Texto Completo: https://repositorio-aberto.up.pt/handle/10216/85031
• topic: Engenharia electrotécnica, Engenharia electrotécnica, electrónica e informática; Electrical engineering, Electrical engineering, Electronic engineering, Information engineering

Dynamically reconfigurable systems have benefited from a new class of FPGAs, recently introduced into the market, that enables partial and dynamic reconfiguration.While enabling concurrent reconfiguration without disturbing the system operation, this technology also raises a new test challenge: to assure a continuously fault-free operation, independently of the circuit present after many reconfiguration processes. A new structural concurrent test method, recently proposed by the authors and based on the principle of replicating and freeing the resources to be tested, raised several questions, one of them being: what strategy to follow in the process of dynamically replicating and freeing those resources?This paper presents a strategy to free the resources to be tested and the results of a series of simulation experiments made with the objective of finding the best methodology to achieve it.