DRAFT: An On-line Concurrent Test for Partial and Dynamically Reconfigurable FPGAs

• Autor(a) principal: Manuel Gericota
• Data de Publicação: 2001
• Outros Autores: Gustavo Costa Alves, Miguel L. Silva, José Martins Ferreira
• Tipo de documento: Livro
• Idioma: eng
• Título da fonte: Repositório Científico de Acesso Aberto de Portugal (Repositórios Cientìficos)
• Texto Completo: https://hdl.handle.net/10216/85053
• topic: Engenharia electrotécnica, Engenharia electrotécnica, electrónica e informática; Electrical engineering, Electrical engineering, Electronic engineering, Information engineering

The use of partial and dynamically reconfigurable FPGAs in reconfigurable systems opens exciting possibilities, since they enable the concurrent reconfiguration of part of the system without interrupting its operation. Nevertheless, larger dies and the use of smaller submicron scales in the manufacturing of this new kind of FPGAs increase the probability of failures after many reconfiguration processes. New methods of test and fault tolerance are therefore required, capable of ensuring system reliability. This paper presents improvements to our RaT Freed Resources technique, a structural concurrent test approach able to detect and diagnose faults without disturbing system operation, throughout its lifetime.