Maze routing steiner trees with delay versus wire length tradeoff
Autor(a) principal: | |
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Data de Publicação: | 2009 |
Outros Autores: | , , |
Tipo de documento: | Artigo |
Idioma: | eng |
Título da fonte: | Repositório Institucional da UFRGS |
Texto Completo: | http://hdl.handle.net/10183/27623 |
Resumo: | In this paper, we address the problem of generating good topologies of rectilinear Steiner trees using path search algorithms. Various techniques have been applied in order to achieve acceptable run times on a Maze Router that builds Steiner trees. A biasing technique proposed for wire length improvement, produces trees that are within 2% from optimal topologies in average. By introducing a sharing factor and a path-length factor we show how to trade-off wire length for delay. Experimental results show that our algorithm generates topologies with better delay compared to state of the art heuristics for Steiner trees, such as AHHK (from 26% to 40%) and P-Trees (from 1% to 30% and from 6% to 21% in the presence of blockages) while keeping the properties of a routing algorithm. An important motivation for this work lies in the fact that it can be used for estimation in the early stages as well as for actual routing, thereby improving the convergence and timing closure of the design significantly.We also provide some valuable theoretical background and insights on delay optimization and on how it relates to our maze router implementation. |
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Hentschke, Renato FernandesNarasimhan, JaganathanJohann, Marcelo de OliveiraReis, Ricardo Augusto da Luz2011-01-29T06:00:44Z20091063-8210http://hdl.handle.net/10183/27623000715665In this paper, we address the problem of generating good topologies of rectilinear Steiner trees using path search algorithms. Various techniques have been applied in order to achieve acceptable run times on a Maze Router that builds Steiner trees. A biasing technique proposed for wire length improvement, produces trees that are within 2% from optimal topologies in average. By introducing a sharing factor and a path-length factor we show how to trade-off wire length for delay. Experimental results show that our algorithm generates topologies with better delay compared to state of the art heuristics for Steiner trees, such as AHHK (from 26% to 40%) and P-Trees (from 1% to 30% and from 6% to 21% in the presence of blockages) while keeping the properties of a routing algorithm. An important motivation for this work lies in the fact that it can be used for estimation in the early stages as well as for actual routing, thereby improving the convergence and timing closure of the design significantly.We also provide some valuable theoretical background and insights on delay optimization and on how it relates to our maze router implementation.application/pdfengIEEE transactions on very large scale integration (VLSI) systems. New York. Vol. 17, no 8 (Aug. 2009), p. 1073-1086MicroeletrônicaVlsiDelayMaze searchRoutingSteiner treesMaze routing steiner trees with delay versus wire length tradeoffEstrangeiroinfo:eu-repo/semantics/articleinfo:eu-repo/semantics/publishedVersioninfo:eu-repo/semantics/openAccessreponame:Repositório Institucional da UFRGSinstname:Universidade Federal do Rio Grande do Sul (UFRGS)instacron:UFRGSTEXT000715665.pdf.txt000715665.pdf.txtExtracted Texttext/plain73522http://www.lume.ufrgs.br/bitstream/10183/27623/2/000715665.pdf.txtf15193dac236d289d6a595a31a065cd2MD52ORIGINAL000715665.pdfTexto completo (inglês)application/pdf1157822http://www.lume.ufrgs.br/bitstream/10183/27623/1/000715665.pdfe963090f3b469618cf9297e73801a388MD5110183/276232021-06-13 04:33:26.423862oai:www.lume.ufrgs.br:10183/27623Repositório de PublicaçõesPUBhttps://lume.ufrgs.br/oai/requestopendoar:2021-06-13T07:33:26Repositório Institucional da UFRGS - Universidade Federal do Rio Grande do Sul (UFRGS)false |
dc.title.pt_BR.fl_str_mv |
Maze routing steiner trees with delay versus wire length tradeoff |
title |
Maze routing steiner trees with delay versus wire length tradeoff |
spellingShingle |
Maze routing steiner trees with delay versus wire length tradeoff Hentschke, Renato Fernandes Microeletrônica Vlsi Delay Maze search Routing Steiner trees |
title_short |
Maze routing steiner trees with delay versus wire length tradeoff |
title_full |
Maze routing steiner trees with delay versus wire length tradeoff |
title_fullStr |
Maze routing steiner trees with delay versus wire length tradeoff |
title_full_unstemmed |
Maze routing steiner trees with delay versus wire length tradeoff |
title_sort |
Maze routing steiner trees with delay versus wire length tradeoff |
author |
Hentschke, Renato Fernandes |
author_facet |
Hentschke, Renato Fernandes Narasimhan, Jaganathan Johann, Marcelo de Oliveira Reis, Ricardo Augusto da Luz |
author_role |
author |
author2 |
Narasimhan, Jaganathan Johann, Marcelo de Oliveira Reis, Ricardo Augusto da Luz |
author2_role |
author author author |
dc.contributor.author.fl_str_mv |
Hentschke, Renato Fernandes Narasimhan, Jaganathan Johann, Marcelo de Oliveira Reis, Ricardo Augusto da Luz |
dc.subject.por.fl_str_mv |
Microeletrônica Vlsi |
topic |
Microeletrônica Vlsi Delay Maze search Routing Steiner trees |
dc.subject.eng.fl_str_mv |
Delay Maze search Routing Steiner trees |
description |
In this paper, we address the problem of generating good topologies of rectilinear Steiner trees using path search algorithms. Various techniques have been applied in order to achieve acceptable run times on a Maze Router that builds Steiner trees. A biasing technique proposed for wire length improvement, produces trees that are within 2% from optimal topologies in average. By introducing a sharing factor and a path-length factor we show how to trade-off wire length for delay. Experimental results show that our algorithm generates topologies with better delay compared to state of the art heuristics for Steiner trees, such as AHHK (from 26% to 40%) and P-Trees (from 1% to 30% and from 6% to 21% in the presence of blockages) while keeping the properties of a routing algorithm. An important motivation for this work lies in the fact that it can be used for estimation in the early stages as well as for actual routing, thereby improving the convergence and timing closure of the design significantly.We also provide some valuable theoretical background and insights on delay optimization and on how it relates to our maze router implementation. |
publishDate |
2009 |
dc.date.issued.fl_str_mv |
2009 |
dc.date.accessioned.fl_str_mv |
2011-01-29T06:00:44Z |
dc.type.driver.fl_str_mv |
Estrangeiro info:eu-repo/semantics/article |
dc.type.status.fl_str_mv |
info:eu-repo/semantics/publishedVersion |
format |
article |
status_str |
publishedVersion |
dc.identifier.uri.fl_str_mv |
http://hdl.handle.net/10183/27623 |
dc.identifier.issn.pt_BR.fl_str_mv |
1063-8210 |
dc.identifier.nrb.pt_BR.fl_str_mv |
000715665 |
identifier_str_mv |
1063-8210 000715665 |
url |
http://hdl.handle.net/10183/27623 |
dc.language.iso.fl_str_mv |
eng |
language |
eng |
dc.relation.ispartof.pt_BR.fl_str_mv |
IEEE transactions on very large scale integration (VLSI) systems. New York. Vol. 17, no 8 (Aug. 2009), p. 1073-1086 |
dc.rights.driver.fl_str_mv |
info:eu-repo/semantics/openAccess |
eu_rights_str_mv |
openAccess |
dc.format.none.fl_str_mv |
application/pdf |
dc.source.none.fl_str_mv |
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Repositório Institucional da UFRGS |
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