A SPICE model for design of threshold current controlled memristive devices based applications
Autor(a) principal: | |
---|---|
Data de Publicação: | 2021 |
Outros Autores: | |
Tipo de documento: | Artigo |
Idioma: | eng |
Título da fonte: | Repositório Institucional da UFRGS |
Texto Completo: | http://hdl.handle.net/10183/224552 |
Resumo: | This paper presents a generic SPICE model for threshold current controlled memristive devices. This work relates to mathematical development to allow this kind of behavior and it exhibits its relationship with the equivalent circuit adopted to achieve this goal. The operating logic is described and the code for its computational implementation is presented and explained. The functionality of the model implemented is demonstrated through several simulation experiments, whose results clearly show the switching resistance dependency on the electrical current through the device and highlight some important fingerprints of memristive devices. The acquisition and the data analysis from tests also help to prove the excellent convergence performance of the model presented and to elucidate the parameter settings. Finally, the paper reinforces the relevance of this new proposition by addressing one of its potential applications, demonstrating its use in the implementation of memristive stateful logic based on material implication. |
id |
UFRGS-2_8b108841b4643a4dd90aa97c0f61594b |
---|---|
oai_identifier_str |
oai:www.lume.ufrgs.br:10183/224552 |
network_acronym_str |
UFRGS-2 |
network_name_str |
Repositório Institucional da UFRGS |
repository_id_str |
|
spelling |
Dias, Cesar de SouzaButzen, Paulo Francisco2021-07-27T04:33:40Z20211573-1979http://hdl.handle.net/10183/224552001128503This paper presents a generic SPICE model for threshold current controlled memristive devices. This work relates to mathematical development to allow this kind of behavior and it exhibits its relationship with the equivalent circuit adopted to achieve this goal. The operating logic is described and the code for its computational implementation is presented and explained. The functionality of the model implemented is demonstrated through several simulation experiments, whose results clearly show the switching resistance dependency on the electrical current through the device and highlight some important fingerprints of memristive devices. The acquisition and the data analysis from tests also help to prove the excellent convergence performance of the model presented and to elucidate the parameter settings. Finally, the paper reinforces the relevance of this new proposition by addressing one of its potential applications, demonstrating its use in the implementation of memristive stateful logic based on material implication.application/pdfengAnalog integrated circuits and signal processing [recurso eletrônico]. Berlin. Vol. 106, no. 1 (Jan. 2021), p. 177–194Circuitos digitaisMicroeletrônicaSimulação computacionalMemristorSPICE modelThreshold currentSwitching resistanceStateful logicMaterial implicationA SPICE model for design of threshold current controlled memristive devices based applicationsEstrangeiroinfo:eu-repo/semantics/articleinfo:eu-repo/semantics/publishedVersioninfo:eu-repo/semantics/openAccessreponame:Repositório Institucional da UFRGSinstname:Universidade Federal do Rio Grande do Sul (UFRGS)instacron:UFRGSTEXT001128503.pdf.txt001128503.pdf.txtExtracted Texttext/plain71695http://www.lume.ufrgs.br/bitstream/10183/224552/2/001128503.pdf.txta91ea976df0f59a12529ba43ecfa6deeMD52ORIGINAL001128503.pdfTexto completo (inglês)application/pdf2473410http://www.lume.ufrgs.br/bitstream/10183/224552/1/001128503.pdf60fd6e76f40aec40a89e61d701f0382fMD5110183/2245522021-09-19 04:34:37.17975oai:www.lume.ufrgs.br:10183/224552Repositório de PublicaçõesPUBhttps://lume.ufrgs.br/oai/requestopendoar:2021-09-19T07:34:37Repositório Institucional da UFRGS - Universidade Federal do Rio Grande do Sul (UFRGS)false |
dc.title.pt_BR.fl_str_mv |
A SPICE model for design of threshold current controlled memristive devices based applications |
title |
A SPICE model for design of threshold current controlled memristive devices based applications |
spellingShingle |
A SPICE model for design of threshold current controlled memristive devices based applications Dias, Cesar de Souza Circuitos digitais Microeletrônica Simulação computacional Memristor SPICE model Threshold current Switching resistance Stateful logic Material implication |
title_short |
A SPICE model for design of threshold current controlled memristive devices based applications |
title_full |
A SPICE model for design of threshold current controlled memristive devices based applications |
title_fullStr |
A SPICE model for design of threshold current controlled memristive devices based applications |
title_full_unstemmed |
A SPICE model for design of threshold current controlled memristive devices based applications |
title_sort |
A SPICE model for design of threshold current controlled memristive devices based applications |
author |
Dias, Cesar de Souza |
author_facet |
Dias, Cesar de Souza Butzen, Paulo Francisco |
author_role |
author |
author2 |
Butzen, Paulo Francisco |
author2_role |
author |
dc.contributor.author.fl_str_mv |
Dias, Cesar de Souza Butzen, Paulo Francisco |
dc.subject.por.fl_str_mv |
Circuitos digitais Microeletrônica Simulação computacional |
topic |
Circuitos digitais Microeletrônica Simulação computacional Memristor SPICE model Threshold current Switching resistance Stateful logic Material implication |
dc.subject.eng.fl_str_mv |
Memristor SPICE model Threshold current Switching resistance Stateful logic Material implication |
description |
This paper presents a generic SPICE model for threshold current controlled memristive devices. This work relates to mathematical development to allow this kind of behavior and it exhibits its relationship with the equivalent circuit adopted to achieve this goal. The operating logic is described and the code for its computational implementation is presented and explained. The functionality of the model implemented is demonstrated through several simulation experiments, whose results clearly show the switching resistance dependency on the electrical current through the device and highlight some important fingerprints of memristive devices. The acquisition and the data analysis from tests also help to prove the excellent convergence performance of the model presented and to elucidate the parameter settings. Finally, the paper reinforces the relevance of this new proposition by addressing one of its potential applications, demonstrating its use in the implementation of memristive stateful logic based on material implication. |
publishDate |
2021 |
dc.date.accessioned.fl_str_mv |
2021-07-27T04:33:40Z |
dc.date.issued.fl_str_mv |
2021 |
dc.type.driver.fl_str_mv |
Estrangeiro info:eu-repo/semantics/article |
dc.type.status.fl_str_mv |
info:eu-repo/semantics/publishedVersion |
format |
article |
status_str |
publishedVersion |
dc.identifier.uri.fl_str_mv |
http://hdl.handle.net/10183/224552 |
dc.identifier.issn.pt_BR.fl_str_mv |
1573-1979 |
dc.identifier.nrb.pt_BR.fl_str_mv |
001128503 |
identifier_str_mv |
1573-1979 001128503 |
url |
http://hdl.handle.net/10183/224552 |
dc.language.iso.fl_str_mv |
eng |
language |
eng |
dc.relation.ispartof.pt_BR.fl_str_mv |
Analog integrated circuits and signal processing [recurso eletrônico]. Berlin. Vol. 106, no. 1 (Jan. 2021), p. 177–194 |
dc.rights.driver.fl_str_mv |
info:eu-repo/semantics/openAccess |
eu_rights_str_mv |
openAccess |
dc.format.none.fl_str_mv |
application/pdf |
dc.source.none.fl_str_mv |
reponame:Repositório Institucional da UFRGS instname:Universidade Federal do Rio Grande do Sul (UFRGS) instacron:UFRGS |
instname_str |
Universidade Federal do Rio Grande do Sul (UFRGS) |
instacron_str |
UFRGS |
institution |
UFRGS |
reponame_str |
Repositório Institucional da UFRGS |
collection |
Repositório Institucional da UFRGS |
bitstream.url.fl_str_mv |
http://www.lume.ufrgs.br/bitstream/10183/224552/2/001128503.pdf.txt http://www.lume.ufrgs.br/bitstream/10183/224552/1/001128503.pdf |
bitstream.checksum.fl_str_mv |
a91ea976df0f59a12529ba43ecfa6dee 60fd6e76f40aec40a89e61d701f0382f |
bitstream.checksumAlgorithm.fl_str_mv |
MD5 MD5 |
repository.name.fl_str_mv |
Repositório Institucional da UFRGS - Universidade Federal do Rio Grande do Sul (UFRGS) |
repository.mail.fl_str_mv |
|
_version_ |
1801225028099899392 |