Super-VLIW: uma arquitetura dinamicamente reconfigurável com tolerância a falha

• Autor(a) principal: Bueno, Cristóferson Guimarães Magalhães
• Data de Publicação: 2011
• Tipo de documento: Dissertação
• Idioma: por
• Título da fonte: LOCUS Repositório Institucional da UFV
• Texto Completo: http://locus.ufv.br/handle/123456789/2622
• topic: Tolerância a falhas; Arquiteturas reconfiguráveis; Tradução Binária; Grão-Grosso; Fault tolerant; Reconfigurable architecture; Binary translation; Coarse-grain; CNPQ::CIENCIAS EXATAS E DA TERRA::CIENCIA DA COMPUTACAO

A new scenario emerges due to nanotechnologies that will enable very high integration at the limits or even beyond silicon capacity. However, the fault rate, which is predicted to range from 1% up to 20% of all devices, could compromise the future of nanotechnologies. This work proposes a fault tolerant reconfigurable architecture that tolerates high fault rates expected to future technologies, named Super-VLIW. The architecture consists of a reconfigurable unit tightly coupled to a MIPS processor. The reconfigurable unit is composed of a binary translation unit, a configuration cache, a reconfigurable coarse-grained array of heterogeneous functional units and an interconnection network. Reconfiguration is done at run-time, by translating the binary code, and no recompilation is needed. The interconnection network is based on a set of multistage networks. These networks provide a fault-tolerant communication between any pair of functional unit and from/to the MIPS register file. This work proposes a mechanism to dynamically allocate the available units to ensure parallel execution of basic operations, performing the placement and routing on a single step, which allows the correct interconnection of units even at huge fault rates. Moreover, the proposed architecture could scale to the future nanotechnologies even under a 20% fault rate.