Redes de interconexão multiestágios em arquiteturas dinamicamente reconfiguráveis de grão grosso acopladas a processadores Risc

• Autor(a) principal: Laure, Marcone Guimarães
• Data de Publicação: 2010
• Tipo de documento: Dissertação
• Idioma: por
• Título da fonte: LOCUS Repositório Institucional da UFV
• Texto Completo: http://locus.ufv.br/handle/123456789/2608
• topic: Arquiteturas reconfiguráveis; Reconfiguração dinâmica; Tradução binária; Redes multiestagios; Aceleradores em Hardware; Reconfigurable architectures; Dynamic reconfiguration; Binary translation; Multistage networks; Hardware accelerators; CNPQ::CIENCIAS EXATAS E DA TERRA::CIENCIA DA COMPUTACAO

Coarse grain reconfigurable architectures are presented as scalable solutions for embedde systems, capable of providing performance and power savings, while the coarse grain reduces memory and reconfiguration time, and reduces the routing and placement complexit. Howerer, even in regular architectures, the interconnection costs in area are high, reaching 50 % oh the area of reconfigurable component. Most os these architectures are two-dimensional and uses fully conectable networks, like multiplexers networks or crossbar, to provide maximum routeability at cost os extra area. This works shows the benefits of using multistage networks, such as low-cost area and low complexity, in architectures with dynamic and trasparent reconfiguration. Besides the saving of 26% in the total area occupied by the reconfigurable unit (RU) with multistage networks before the RU with multiplexers networks of multiplexers, a new model of RU, one-dimensional is proposed, which is even more compact. At the same time that the area of RU is reduced, the flexibility to accelerate heterogeneous applications is maintained.