Winner-take-all circuit using CMOS technology

Detalhes bibliográficos
Autor(a) principal: Oki, N.
Data de Publicação: 1999
Tipo de documento: Artigo de conferência
Idioma: eng
Título da fonte: Repositório Institucional da UNESP
Texto Completo: http://dx.doi.org/10.1109/MWSCAS.1998.759556
http://hdl.handle.net/11449/9667
Resumo: In this paper is presented an implementation of winner-take-all circuit using CMOS technology. In the proposed configuration the inputs are current and the outputs voltage. The simulation results show that the circuit can be a winner if its input is larger than the other by 2 mu A. The simulation also shows that the response time is 100ns at a 0.2pF load capacitance. To demonstrate the functionality of the proposed circuit, a two-input winner take all circuit was built and tested by using discrete CMOS transistor array (CD40071).
id UNSP_156aa9cee9342bf97bd34e52e7a85c52
oai_identifier_str oai:repositorio.unesp.br:11449/9667
network_acronym_str UNSP
network_name_str Repositório Institucional da UNESP
repository_id_str 2946
spelling Winner-take-all circuit using CMOS technologyIn this paper is presented an implementation of winner-take-all circuit using CMOS technology. In the proposed configuration the inputs are current and the outputs voltage. The simulation results show that the circuit can be a winner if its input is larger than the other by 2 mu A. The simulation also shows that the response time is 100ns at a 0.2pF load capacitance. To demonstrate the functionality of the proposed circuit, a two-input winner take all circuit was built and tested by using discrete CMOS transistor array (CD40071).UNESP, FEIS, DEE, São Paulo, BrazilUNESP, FEIS, DEE, São Paulo, BrazilIEEE Computer SocUniversidade Estadual Paulista (Unesp)Oki, N.2014-05-20T13:28:56Z2014-05-20T13:28:56Z1999-01-01info:eu-repo/semantics/publishedVersioninfo:eu-repo/semantics/conferenceObject568-570http://dx.doi.org/10.1109/MWSCAS.1998.7595561998 Midwest Symposium on Circuits and Systems, Proceedings. Los Alamitos: IEEE Computer Soc, p. 568-570, 1999.http://hdl.handle.net/11449/966710.1109/MWSCAS.1998.759556WOS:0000795632001321525717947689076Web of Sciencereponame:Repositório Institucional da UNESPinstname:Universidade Estadual Paulista (UNESP)instacron:UNESPeng1998 Midwest Symposium on Circuits and Systems, Proceedingsinfo:eu-repo/semantics/openAccess2024-07-04T19:11:44Zoai:repositorio.unesp.br:11449/9667Repositório InstitucionalPUBhttp://repositorio.unesp.br/oai/requestopendoar:29462024-08-05T19:53:06.604338Repositório Institucional da UNESP - Universidade Estadual Paulista (UNESP)false
dc.title.none.fl_str_mv Winner-take-all circuit using CMOS technology
title Winner-take-all circuit using CMOS technology
spellingShingle Winner-take-all circuit using CMOS technology
Oki, N.
title_short Winner-take-all circuit using CMOS technology
title_full Winner-take-all circuit using CMOS technology
title_fullStr Winner-take-all circuit using CMOS technology
title_full_unstemmed Winner-take-all circuit using CMOS technology
title_sort Winner-take-all circuit using CMOS technology
author Oki, N.
author_facet Oki, N.
author_role author
dc.contributor.none.fl_str_mv Universidade Estadual Paulista (Unesp)
dc.contributor.author.fl_str_mv Oki, N.
description In this paper is presented an implementation of winner-take-all circuit using CMOS technology. In the proposed configuration the inputs are current and the outputs voltage. The simulation results show that the circuit can be a winner if its input is larger than the other by 2 mu A. The simulation also shows that the response time is 100ns at a 0.2pF load capacitance. To demonstrate the functionality of the proposed circuit, a two-input winner take all circuit was built and tested by using discrete CMOS transistor array (CD40071).
publishDate 1999
dc.date.none.fl_str_mv 1999-01-01
2014-05-20T13:28:56Z
2014-05-20T13:28:56Z
dc.type.status.fl_str_mv info:eu-repo/semantics/publishedVersion
dc.type.driver.fl_str_mv info:eu-repo/semantics/conferenceObject
format conferenceObject
status_str publishedVersion
dc.identifier.uri.fl_str_mv http://dx.doi.org/10.1109/MWSCAS.1998.759556
1998 Midwest Symposium on Circuits and Systems, Proceedings. Los Alamitos: IEEE Computer Soc, p. 568-570, 1999.
http://hdl.handle.net/11449/9667
10.1109/MWSCAS.1998.759556
WOS:000079563200132
1525717947689076
url http://dx.doi.org/10.1109/MWSCAS.1998.759556
http://hdl.handle.net/11449/9667
identifier_str_mv 1998 Midwest Symposium on Circuits and Systems, Proceedings. Los Alamitos: IEEE Computer Soc, p. 568-570, 1999.
10.1109/MWSCAS.1998.759556
WOS:000079563200132
1525717947689076
dc.language.iso.fl_str_mv eng
language eng
dc.relation.none.fl_str_mv 1998 Midwest Symposium on Circuits and Systems, Proceedings
dc.rights.driver.fl_str_mv info:eu-repo/semantics/openAccess
eu_rights_str_mv openAccess
dc.format.none.fl_str_mv 568-570
dc.publisher.none.fl_str_mv IEEE Computer Soc
publisher.none.fl_str_mv IEEE Computer Soc
dc.source.none.fl_str_mv Web of Science
reponame:Repositório Institucional da UNESP
instname:Universidade Estadual Paulista (UNESP)
instacron:UNESP
instname_str Universidade Estadual Paulista (UNESP)
instacron_str UNESP
institution UNESP
reponame_str Repositório Institucional da UNESP
collection Repositório Institucional da UNESP
repository.name.fl_str_mv Repositório Institucional da UNESP - Universidade Estadual Paulista (UNESP)
repository.mail.fl_str_mv
_version_ 1808129134232076288

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